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july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. am70pdl127cdh/ am70pdl129cdh data sheet publication number 30651 revision a amendment +2 issue date november 24, 2003
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advance information this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 30651 rev: a amendment +2 issue date: november 24, 2003 refer to amd?s website (www.amd.com) for the latest information. am70pdl127cdh/am70pdl129cdh stacked multi-chip packag e (mcp/xip) flash memory, data storage mirrorbit flash, and psram (xip) 2 x 64 megabit (8 m x 16-bit) cmos 3.0 volt-only page mode flash memory data storage 128 megabit (8 m x 16-bit) cmos 3.0 volt-only, simultaneous operation flash memory and 64 mbit (4 m x 16-bit) cmos pseudo static ram distinctive characteristics mcp features consists of am29pdl127h/am29pdl129h, 64 mb psram and two am29lv640m. power supply voltage of 2.7 to 3.1 volt high performance (xip) ? access time as fast as 65 ns initial / 25 ns page high performance (data storage) ? access time as fast as 110 ns initial / 30 ns page package ? 93-ball fbga operating temperature ? ?40c to +85c flash memory features (xip) am29pdl127h/am29pdl129h architectural advantages 128 mbit page mode device ? page size of 8 words: fast page read access from random locations within the page dual chip enable inputs (pdl129 only) ? two ce# inputs control selection of each half of the memory space single power supply operation ? full voltage range: 2.7 to 3.1 volt read, erase, and program operations for battery-powered applications simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency switching from write to read operations flexbank architecture ? 4 separate banks, with up to two simultaneous operations per device pdl127: ? bank a: 16 mbit (4 kw x 8 and 32 kw x 31) ? bank b: 48 mbit (32 kw x 96) ? bank c: 48 mbit (32 kw x 96) ? bank d: 16 mbit (4 kw x 8 and 32 kw x 31) pdl129: ? bank 1a: 48 mbit (32 kw x 96) ? bank 1b: 16 mbit (4 kw x 8 and 32 kw x 31) ? bank 2a: 16 mbit (4 kw x 8 and 32 kw x 31) ? bank 2b: 48 mbit (32 kw x 96) secsi tm (secured silicon) sector region ? up to 128 words accessible through a command sequence ? up to 64 factory-locked words ? up to 64 customer-lockable words both top and bottom boot blocks in one device manufactured on 0.13 m process technology 20-year data retention at 125c minimum 1 million erase cycle guarantee per sector performance characteristics high performance ? page access times as fast as 25 ns ? random access times as fast as 65 ns power consumption (typical values at 10 mhz) ? 45 ma active read current ? 25 ma program/erase current ? 1 a typical standby mode current software features software command-set compatible with jedec 42.4 standard ? backward compatible with am29f and am29lv families cfi (common flash interface) complaint ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices erase suspend / erase resume ? suspends an erase operation to allow read or program operations in other sectors of same bank unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion hardware reset pin (reset#) ? hardware method to reset the device to reading array data
2 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information wp#/acc (write protect/acceleration) input ?at v il , hardware level protection for the first and last two 4k word sectors. ?at v ih , allows removal of sector protection ?at v hh , provides accelerated programming in a factory setting flash memory features (data storage) am29lv640m architectural advantages single power supply operation ? 3 v for read, erase, and program operations manufactured on 0.23 m mirrorbit process technology secsi ? (secured silicon) sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer flexible sector architecture ? one hundred twenty-eight 32 kword sectors compatibility with jedec standards ? provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125 c performance characteristics high performance ? 110 ns access time ? 30 ns page read times ? 0.5 s typical sector erase time ? 22 s typical effective write buffer word programming time: 16-word write buffer reduces overall programming time for multiple-word updates ? 4-word page read buffer ? 16-word write buffer low power consumption (typical values at 3.0 v, 5 mhz) ? 30 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current software & hardware features software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector unprotect: v id -level method of changing code in locked sectors ? wp#/acc input: write protect input (wp#) protects first or last sector regardless of sector protection settings acc (high voltage) accelerates programming time for higher throughput during system production ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) indicates program or erase cycle completion
november 24, 2003 am70pdl127cdh/am70pdl129cdh 3 advance information psram features power dissipation ? operating: 35 ma maximum ? standby: 80 a maximum ? deep power-down standby: 20 a data retention supply voltage: 2.7 to 3.1 v power down features using ce#1s and ce2s ce1s# and ce2s chip select byte data control: lb#s (dq7-dq0), ub#s (dq15-dq8)
4 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information general description (pdl129) the am29pdl129h is a 128 mbit, 3.0 volt-only page mode and simultaneous read/write flash memory device orga- nized as 8 mwords. the word-wide data (x16) appears on dq15-dq0. this device can be programmed in-system or in standard eprom programmers. a 12.0 v v pp is not required for write or erase operations. the device offers fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to oper- ate without wait states. to eliminate bus contention the de- vice has separate chip enable (ce#f1, ce#f2), write enable (we#) and output enable (oe#) controls. dual chip enables allow access to two 64 mbit partitions of the 128 mbit mem- ory space. simultaneous read/write operation with zero latency the simultaneous read/write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. the de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). this releases the system from waiting for the completion of a program or erase operation, greatly improv- ing system performance. the device can be organized in both top and bottom sector configurations. the banks are organized as follows: page mode features the page size is 8 words. after initial page access is accom- plished, the page mode operation provides fast read access speed of random locations within that page. standard flash memory features the device requires a single 3.0 volt power supply (2.7 v to 3.1 v) for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec 42.4 single-power-supply flash standard . com- mands are written to the command register using standard microprocessor write timing. register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch ad- dresses and data needed for the programming and erase operations. reading data out of the device is similar to read- ing from other flash or eprom devices. device programming occurs by executing the program com- mand sequence. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to pro- gram data instead of four. device erasure occurs by execut- ing the erase command sequence. the host system can detect whether a program or erase op- eration is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc de- tector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secsi sector area (one time pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the device offers two power-saving features. when ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode. power con- sumption is greatly reduced in both these modes. amd?s flash technology combined years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electri- cally erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection. chip enable configuration ce#f1 control ce#f2 control bank 1a 48 mbit (32 kw x 96) bank 2a 16 mbit (4 kw x 8 and 32 kw x 31) bank 1b 16 mbit (4 kw x 8 and 32 kw x 31) bank 2b 48 mbit (32 kw x 96)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 5 advance information general description (pdl127) the am29pdl127h is a 128 mbit, 3.0 volt-only page mode and simultaneous read/write flash memory device orga- nized as 8 mwords. the word-wide data (x16) appears on dq15-dq0. this device can be programmed in-system or in standard eprom programmers. a 12.0 v v pp is not required for write or erase operations. the device offers fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to oper- ate without wait states. to eliminate bus contention the de- vice has separate chip enable (ce#f1), write enable (we#) and output enable (oe#) controls. simultaneous read/write operation with zero latency the simultaneous read/write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. the de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). this releases the system from waiting for the completion of a program or erase operation, greatly improv- ing system performance. the device can be organized in both top and bottom sector configurations. the banks are organized as follows: page mode features the page size is 8 words. after initial page access is accom- plished, the page mode operation provides fast read access speed of random locations within that page. standard flash memory features the device requires a single 3.0 volt power supply (2.7 v to 3.1 v) for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec 42.4 single-power-supply flash standard . com- mands are written to the command register using standard microprocessor write timing. register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch ad- dresses and data needed for the programming and erase operations. reading data out of the device is similar to read- ing from other flash or eprom devices. device programming occurs by executing the program com- mand sequence. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to pro- gram data instead of four. device erasure occurs by execut- ing the erase command sequence. the host system can detect whether a program or erase op- eration is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc de- tector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secsi sector area (one time pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the device offers two power-saving features. when ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode. power con- sumption is greatly reduced in both these modes. amd?s flash technology combined years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electri- cally erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection. bank sectors a 16 mbit (4 kw x 8 and 32 kw x 31) b 48 mbit (32 kw x 96) c 48 mbit (32 kw x 96) d 16 mbit (4 kw x 8 and 32 kw x 31)
6 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 9 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . 9 connection diagram?pdl129h . . . . . . . . . . . . . . 10 special package handling instructions .................................. 10 connection diagram?pdl127h . . . . . . . . . . . . . . 11 special package handling instructions .................................. 11 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ordering information . . . . . . . . . . . . . . . . . . . . . . 13 requirements for reading array data ................................... 16 random read (non-page read) ........................................ 16 page mode read ................................................................ 16 table 2. page select .......................................................................16 simultaneous operation ......................................................... 16 table 3. bank select (pdl129h) ....................................................16 table 4. bank select (pdl127h) ....................................................16 writing commands/command sequences ............................ 17 accelerated program operation .......................................... 17 autoselect functions ........................................................... 17 standby mode ........................................................................ 17 automatic sleep mode ........................................................... 17 reset#: hardware reset pin ............................................... 18 output disable mode .............................................................. 18 table 5. secsi tm sector addresses ................................................18 table 6. am29pdl127h sector architecture ..................................19 table 7. am29pdl129h sector architecture ..................................26 table 8. am29pdl127h boot sector/sector block addresses for pro- tection/unprotection ........................................................................34 table 9. am29pdl129h boot sector/sector block addresses for pro- tection/unprotection ce#f1 control ..................................................................................35 table 10. am29pdl129h boot sector/sector block addresses for protection/unprotection ce#f2 control ..................................................................................35 sector protection . . . . . . . . . . . . . . . . . . . . . . . . . 36 persistent sector protection ................................................... 36 persistent protection bit (ppb) ............................................ 36 persistent protection bit lock (ppb lock) .......................... 36 dynamic protection bit (dyb) ............................................. 36 table 11. sector protection schemes .............................................37 persistent sector protection mode locking bit ................... 37 password protection mode ..................................................... 37 password and password mode locking bit ........................ 38 64-bit password ................................................................... 38 write protect (wp#) ................................................................ 38 persistent protection bit lock .............................................. 38 high voltage sector protection .............................................. 39 figure 1. in-system sector protection/ sector unprotection algorithms ...................................................... 40 temporary sector unprotect .................................................. 41 figure 2. temporary sector unprotect operation........................... 41 secsi? (secured silicon) sector flash memory region ............................................................ 41 factory-locked area (64 words) ......................................... 41 customer-lockable area (64 words) ................................... 41 figure 3. pdl127/9h secsi sector protection algorithm ............... 42 secsi sector protection bits ................................................ 42 hardware data protection ...................................................... 43 low vcc write inhibit ......................................................... 43 write pulse ?glitch? protection ............................................ 43 logical inhibit ....................................................................... 43 power-up write inhibit ......................................................... 43 command definitions . . . . . . . . . . . . . . . . . . . . . 47 reading array data ................................................................ 47 reset command ..................................................................... 47 autoselect command sequence ............................................ 47 enter secsi? sector/exit secsi sector command sequence .............................................................. 48 word program command sequence ...................................... 48 unlock bypass command sequence .................................. 48 figure 4. program operation ......................................................... 49 chip erase command sequence ........................................... 49 sector erase command sequence ........................................ 49 figure 5. erase operation.............................................................. 50 erase suspend/erase resume commands ........................... 50 password program command ................................................ 50 password verify command .................................................... 51 password protection mode locking bit program command .. 51 persistent sector protection mode locking bit program com- mand ....................................................................................... 51 secsi sector protection bit program command .................... 51 ppb lock bit set command ................................................... 51 dyb write command ............................................................. 51 password unlock command .................................................. 52 ppb program command ........................................................ 52 all ppb erase command ........................................................ 52 dyb write command ............................................................. 52 ppb lock bit set command ................................................... 52 ppb status command ............................................................ 52 ppb lock bit status command .............................................. 52 sector protection status command ....................................... 52 command definitions tables .................................................. 53 table 16. memory array command definitions ............................. 53 table 17. sector protection command definitions ........................ 54 write operation status . . . . . . . . . . . . . . . . . . . . 55 dq7: data# polling ................................................................. 55 figure 6. data# polling algorithm .................................................. 55 ry/by#: ready/busy# ............................................................ 56 dq6: toggle bit i .................................................................... 56 figure 7. toggle bit algorithm........................................................ 56 dq2: toggle bit ii ................................................................... 57 reading toggle bits dq6/dq2 ............................................... 57 dq5: exceeded timing limits ................................................ 57 dq3: sector erase timer ....................................................... 57 table 18. write operation status ................................................... 58 absolute maximum ratings . . . . . . . . . . . . . . . . 59 figure 8. maximum negative overshoot waveform ...................... 59 figure 9. maximum positive overshoot waveform........................ 59 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60 psram dc characteristics . . . . . . . . . . . . . . . . . 61 recommended dc operating conditions (note 1) ................ 61 capacitance (f= 1mhz, ta = 25c) ....................................... 61 dc and operating characteristics .......................................... 61 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 10. test setup, vio = 2.7 ? 3.1 v ...................................... 62 figure 11. input waveforms and measurement levels ................. 62
november 24, 2003 am70pdl127cdh/am70pdl129cdh 7 advance information hardware reset (reset#) .................................................... 63 figure 12. reset timings ................................................................ 63 erase and program operations .............................................. 64 figure 13. program operation timings........................................... 65 figure 14. accelerated program timing diagram........................... 65 figure 15. chip/sector erase operation timings ........................... 66 figure 16. back-to-back read/write cycle timings ....................... 67 figure 17. data# polling timings (during embedded algorithms).. 67 figure 18. toggle bit timings (during embedded algorithms)....... 68 figure 19. dq2 vs. dq6.................................................................. 68 temporary sector unprotect .................................................. 69 figure 20. temporary sector unprotect timing diagram ............... 69 figure 21. sector/sector block protect and unprotect timing diagram .............................................................. 70 alternate ce#f1 controlled erase and program operations .. 71 figure 22. flash alternate ce#f1 controlled write (erase/program) operation timings........................................................................... 72 psram ac characteristics . . . . . . . . . . . . . . . . . 73 ce#s timing ........................................................................... 73 figure 23. timing diagram for alternating between pseudo sram to flash.................................................... 73 figure 24. timing waveform of power-up ...................................... 73 psram ac characteristics . . . . . . . . . . . . . . . . . 74 functional description ............................................................ 74 absolute maximum ratings .................................................... 74 figure 25. standby mode state machines ...................................... 75 standby mode characteristic ................................................. 75 ac characteristics (vcc= 2.7-3.1 v, ta= -40 to 85c) ......... 75 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 26. timing waveform of read cycle 1 ................................ 76 figure 27. timing waveform of read cycle 2 ................................ 76 figure 28. timing waveform of write cycle 1 ................................ 77 figure 29. timing waveform of write cycle 2 ................................ 77 figure 30. timing waveform of write cycle 3 ................................ 78 erase and programming performance . . . . . . . . 79 latchup characteristics . . . . . . . . . . . . . . . . . . . 79 package pin capacitance . . . . . . . . . . . . . . . . . . 79 flash data retention . . . . . . . . . . . . . . . . . . . . . . 79 device bus operations . . . . . . . . . . . . . . . . . . . . . 81 table 1. device bus operations .....................................................81 requirements for reading array data ................................... 81 page mode read ................................................................ 82 writing commands/command sequences ............................ 82 write buffer ......................................................................... 82 accelerated program operation .......................................... 82 autoselect functions ........................................................... 82 standby mode ........................................................................ 82 automatic sleep mode ........................................................... 82 reset#: hardware reset pin ............................................... 83 output disable mode .............................................................. 83 table 2. sector address table ........................................................84 sector group protection and unprotection ............................. 87 table 3. sector group protection/unprotection address table .....87 write protect (wp#) ................................................................ 88 temporary sector group unprotect ....................................... 88 figure 1. temporary sector group unprotect operation................ 88 figure 2. in-system sector group protect/unprotect algorithms ... 89 secsi (secured silicon) sector flash memory region .......... 90 table 4. secsi sector contents ......................................................90 figure 3. secsi sector protect verify.............................................. 90 hardware data protection ...................................................... 90 low vcc write inhibit ......................................................... 91 write pulse ?glitch? protection ............................................ 91 logical inhibit ....................................................................... 91 power-up write inhibit ......................................................... 91 common flash memory interface (cfi) . . . . . . . 91 command definitions. . . . . . . . . . . . . . . . . . . . . . 94 reading array data ................................................................ 94 reset command ..................................................................... 95 autoselect command sequence ............................................ 95 enter secsi sector/exit secsi sector command sequence .. 95 word program command sequence ...................................... 95 unlock bypass command sequence .................................. 96 write buffer programming ................................................... 96 accelerated program ........................................................... 97 figure 4. write buffer programming operation.............................. 98 figure 5. program operation ......................................................... 99 program suspend/program resume command sequence ... 99 figure 6. program suspend/program resume............................ 100 chip erase command sequence ......................................... 100 sector erase command sequence ...................................... 100 figure 7. erase operation............................................................ 101 erase suspend/erase resume commands ......................... 101 command definitions ........................................................... 102 write operation status . . . . . . . . . . . . . . . . . . . 103 dq7: data# polling ............................................................... 103 figure 8. data# polling algorithm ................................................ 103 ry/by#: ready/busy# .......................................................... 104 dq6: toggle bit i .................................................................. 104 figure 9. toggle bit algorithm...................................................... 105 dq2: toggle bit ii ................................................................. 105 reading toggle bits dq6/dq2 ............................................. 105 dq5: exceeded timing limits .............................................. 106 dq3: sector erase timer ..................................................... 106 dq1: write-to-buffer abort ................................................... 106 table 10. write operation status ................................................. 106 figure 10. maximum negative overshoot waveform ................. 107 figure 11. maximum positive overshoot waveform................... 107 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 108 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 12. test setup.................................................................. 109 table 11. test specifications ....................................................... 109 key to switching waveforms. . . . . . . . . . . . . . . 109 figure 13. input waveforms and measurement levels.................................................................... 109 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . 110 read-only operations ......................................................... 110 figure 14. read operation timings ............................................. 110 figure 15. page read timings .................................................... 111 hardware reset (reset#) .................................................. 112 figure 16. reset timings ............................................................. 112 erase and program operations ............................................ 113 figure 17. program operation timings........................................ 114 figure 18. accelerated program timing diagram ........................ 114 figure 19. chip/sector erase operation timings ........................ 115 figure 20. data# polling timings (during embedded algorithms) 116 figure 21. toggle bit timings (during embedded algorithms) .... 117 figure 22. dq2 vs. dq6............................................................... 117 temporary sector unprotect ................................................ 118 figure 23. temporary sector group unprotect timing diagram . 118
8 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information figure 24. sector group protect and unprotect timing diagram . 119 alternate ce# controlled erase and program operations ... 120 figure 25. alternate ce# controlled write (erase/program) operation timings......................................................................... 121 erase and programming performance . . . . . . . 122 latchup characteristics . . . . . . . . . . . . . . . . . . 122 package pin capacitance. . . . . . . . . . . . . . . . . . 123 physical dimensions . . . . . . . . . . . . . . . . . . . . . 124 fua093?93-ball fine-pitch grid array 13 x 9 mm package 124 revision summary . . . . . . . . . . . . . . . . . . . . . . . 125
november 24, 2003 am70pdl127cdh/am70pdl129cdh 9 advance information product selector guide mcp block diagram part number am70pdl127cdh/am70pdl129cdh speed option standard voltage range: v cc = 2.7?3.1 v flash memory (xip) pseudo sram flash memory (data storage) 66 85 66 85 66 85 max access time, ns 65 85 70 70 110 110 page access time, ns 25 30 n/a n/a 30 30 ce#f1 access, ns 65 85 70 70 110 110 oe# access, ns 25 30 35 35 30 30 v ss v cc ps reset# we# oe# ce1#ps lb#s ub#s wp#/acc ce2ps 64 mbit pseudo sram 128 mbit flash memory (xip) am29pdl127h/ am29pdl129h dq15 to dq0 dq15 to dq0 a21 to a0 (a22) a21 to a0 ce#f1 ry/by# a21 to a0 (a22 pdl127 only) dq15 to dq0 ce#f2 (pdl129 only) v ss v cc f reset#ds wp#/accds ce#1ds 64 mbit flash memory (data storage) am29lv640mh 64 mbit flash memory (data storage) am29lv640mh ce#2ds v ss v cc qds v ss v cc qds ry/by#ds ry/by#ds dq15 to dq0 dq15 to dq0 a21 to a0 a21 to a0
10 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information connection diagram?pdl129h special package handling instructions special handling is required for flash memory products in molded packages (bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc ce#2ds v cc qf nc a3 a2 a1 a0 ce#f1 ce#1ps a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 ce#f2 wp#/acc reset# ry/by# dq3 v cc f dq11 v cc ds we# ce2ps a20 dq4 v cc ps v cc qds a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 nc dq15 dq7 dq14 a15 a21 nc a16 v cc f v ss nc nc nc nc nc nc flash 1 only b2 c2 nc nc b9 c9 ry/by#ds ce#1ds b3 b4 b7 b8 v ss ds nc reset#ds nc f5 g5 f6 g6 nc nc nc nc k2 l2 l3 l4 nc nc nc v ss ds l7 l8 k9 l9 nc nc wp#/accds nc mirrorbit only ram only flash shared only 93-ball fbga top view
november 24, 2003 am70pdl127cdh/am70pdl129cdh 11 advance information connection diagram?pdl127h special package handling instructions special handling is required for flash memory prod- ucts in molded packages (bga). the pack age and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc ce#2ds v cc qf nc a3 a2 a1 a0 ce#f1 ce#1ps a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 v cc ds we# ce2ps a20 dq4 v cc ps v cc qds a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 nc dq15 dq7 dq14 a15 a21 a22 a16 v cc f v ss nc nc nc nc nc nc flash 1 only b2 c2 nc nc b9 c9 ry/by#ds ce#1ds b3 b4 b7 b8 v ss ds nc reset#ds nc f5 g5 f6 g6 nc nc nc nc k2 l2 l3 l4 nc nc nc v ss ds l7 l8 k9 l9 nc nc wp#/accds nc mirrorbit only ram only 93-ball fbga top view
12 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information pin description a21?a0 = 22 address inputs (common) a22 = address input (pdl127 only) (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f1 = chip enable 1 (flash) ce#f2 = chip enable 2 (flash) (pdl129 only) ce#1ps = chip enable 1 (psram) ce2ps = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output and open drain. when ry/by# = v ih , the device is ready to accept read operations and commands. when ry/by# = vol, the device is either executing an em- bedded algorithm or the device is executing a hardware reset opera- tion. ub#s = upper byte control (psram) lb#s = lower byte control (psram) reset# = hardware reset pin, active low wp#/acc = write protect/acceleration input. when wp/acc#= v il , the highest and lowest two 4k-word sectors are write protected regardless of other sector protection configurations. when wp/acc#= v ih , these sector are unprotected unless the dyb or ppb is programmed. when wp/acc#= 12v, program and erase operations are accelerated. v cc f = flash 3.0 volt-only single power sup- ply (see product selector guide for speed options and voltage supply tolerances) v cc s = psram power supply v ss = device ground (common) ds = data storage nc = pin not connected internally ce#1ds = chip enable 1 (am29lv640mh flash- data storage) ce#2ds = chip enable 2 (am29lv640mh flash- data storage) ry/by# = ready/busy output (data stor- age) reset#ds = hardware reset pin, active low (data storage) wp#/accds = write protect/acceleration input (data storage) logic symbol 22 16 dq15?dq0 a21?a0 ce#f1 oe# we# reset# ub#s ry/by# wp#/acc lb#s ce#1ps ce2ps ce#f2 (pdl129 only) a22 (pdl127 only) ce#2ds reset#ds ce#1ds wp#/accds ry/by#ds
november 24, 2003 am70pdl127cdh/am70pdl129cdh 13 advance information ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. am70pdl12 7c dh66i t tape and reel t = 7 inches s = 13 inches temperature range i = industrial (?40 c to +85 c) speed option see ?product selector guide? on page 9. process technology h = 0.13 m (am29pdl127h and am29pdl129h) 128 mb data storage (2 x am29lv640m) pseudo sram device density c = 64 mbits control pins 7 = 1 ce flash 9 = 2 ce flash amd device number/description am70pdl127cdh/am70pdl129cdh stacked multi-chip package (mcp) flash memory and psram 128 megabit (8 m x 16-bit) cmos 3.0 volt-only, si multaneous operation flash memory and 64 mbit (4 m x 16-bit) pseudo static ram, and 128 mbit data storage. valid combinations order number package marking am70pdl127cdh66i t, s m700000004 am70pdl127cdh85i t, s m700000005 am70pdl129cdh66i t, s m700000006 am70pdl129cdh85i t, s m700000007
14 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information mcp device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 15 advance information table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sadd = flash sector address, a in = address in, d in = data in, d out = data out notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f1 or 2 = v il , ce#1ps = v il and ce2ps = v ih at the same time. 3. don?t care or open lb#s or ub#s. 4. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 5. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector/sector block protection and unprotection? section. 6. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection and unprotection?. if wp#/acc = v hh, all sectors will be unprotected. 7. data will be retained in psram. 8. data will be lost in psram. 9. both ce#f1 inputs may be held low for this operation. operation (notes 1, 2) ce#f1 active ce#f2 (pdl129 only) ce#1ps ce2ps oe# we# addr. lb#s (note 3) ub#s (note 3) reset# wp#/ acc (note 4) dq7? dq0 dq15? dq8 read from active flash (note 7) l (h) h (l) hh lh a in xx h l/h d out d out (note 8) h l write to active flash (note 7) l (h) h (l) hh hl a in xx h (note 4) d in d in (note 8) h l standby v cc 0.3 v hhxxx xx v cc 0.3 v h high-z high-z deep power-down standby v cc 0.3 v hlxxxxx v cc 0.3 v h high-z high-z output disable (note 9) l (h) h (l) l h hh x x x h l/h high-z high-z hh x x x flash hardware reset (note 7) x hh x x x x x l l/h high-z high-z (note 8) h l sector protect (notes 6, 10) (note 7) l (h) h (l) hh hl sadd, a6 = l, a1 = h, a0 = l xx v id l/h d in x (note 9) h l sector unprotect (notes 5, 9) (note 7) l (h) h (l) hh hl sadd, a6 = h, a1 = h, a0 = l xx v id (note 6) d in x (note 8) h l temporary sector unprotect (note 7) x hh xx x x x v id (note 6) d in high-z (note 8) h l read from psram h h l h l h a in ll hx d out d out h l high-z d out lh d out high-z write to psram h h l h x l a in ll hx d in d in h l high-z d in lh d in high-z
16 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information requirements for reading array data to read array data from the outputs, the system must drive the oe# and appropriate ce#f1/ce#f2 (pdl129 only) pins to v il . ce#f1 and ce#f2 are the power con- trol. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. refer to the flash ac characteristics table for timing specifications and to figure 12 for the timing diagram. i cc1 in the dc characteristics table represents the ac- tive current specification for reading array data. random read (non-page read) address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad- dresses and stable ce#f1 to valid data at the output inputs. the output enable access time is the delay from the falling edge of the oe# to valid data at the output inputs (assuming the addresses have been sta- ble for at least t acc ?t oe time). page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. address bits a22?a3 (a21?a3 for pdl129) select an 8-word page, and address bits a2?a0 select a specific word within that page. this is an asynchronous operation with the microprocessor supplying the specific word location. the random or initial page access is t acc or t ce and subsequent page read accesses (as long as the loca- tions specified by the microprocessor fall within that page) are t pac c . when ce#f1 and ce#f2 (pdl129 only) are deasserted (ce#f1=ce#f2=v ih ), the reasser- tion of ce#f1 or ce#f2 (pdl129 only) for subsequent access has access time of t acc or t ce . here again, ce#f1/ce#f2 (pdl129 only) selects the device and oe# is the output control and should be used to gate data to the output inputs if the device is selected. fast page mode accesses are obtained by keeping a22?a3 (a21?a3 for pdl129) constant and changing a2 to a0 to select the specific word within that page. table 2. page select simultaneous operation in addition to the conventional features (read, pro- gram, erase-suspend read, and erase-suspend pro- gram), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), the bank can be selected by bank ad- dresses (a22?a20) (a21?a20 for pdl129) with zero latency. the simultaneous operation can execute multi-func- tion mode in the same bank. table 3. bank select (pdl129h) table 4. bank select (pdl127h) word a2 a1 a0 word 0 000 word 1 001 word 2 010 word 3 011 word 4 100 word 5 101 word 6 110 word 7 111 bank ce#f1 ce#f2 a21?a20 bank 1a 0 1 00, 01, 10 bank 1b 0 1 11 bank 2a 1 0 00 bank 2b 1 0 01, 10, 11 bank a22?a20 bank a 000 bank b 001, 010, 011 bank c 100, 101, 110 bank d 111
november 24, 2003 am70pdl127cdh/am70pdl129cdh 17 advance information writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce#f1 or ce#f2 (pdl 129 only) to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once a bank enters the un- lock bypass mode, only two write cycles are required to program a word, instead of four. the ?word pro- gram command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. ta bl e 4 indicates the address space that each sector occupies. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? refers to the address bits required to uniquely select a sector. the ?command definitions? section has details on erasing a sector or the entire chip, or suspending/resuming the erase op- eration. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the flash ac characteristics section contains timing specifica- tion tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this function is primarily in- tended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that v hh must not be asserted on wp#/acc for operations other than accelerated pro- gramming, or device damage may result. in addition, the wp#/acc pin should be raised to v cc when not in use. that is, the wp#/acc pin should not be left float- ing or unconnected; inconsistent behavior of the de- vice may result. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq15?dq0. standard read cycle timings apply in this mode. refer to the autoselect command se- quence sections for more information. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce#f1, ce#f2 (pdl129 only) and reset# pins are all held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce#f1, ce#f2 (pdl129 only), and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. icc3 in the dc characteristics table represents the cmos standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 150 ns. the automatic sleep mode is independent of the ce#f1/ce#f2 (pdl129 only), we#, and oe# con- trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always avail- able to the system. note that during automatic sleep mode, oe# must be at v ih before the device reduces current to the stated sleep mode specification. icc5 in the dc characteristics table represents the automatic sleep mode current specification.
18 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (icc4). if reset# is held at v il but not within v ss 0.3 v, the standby cur- rent will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase op- eration, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the sys- tem can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the re- set# pin returns to v ih . refer to the psram ac characteristics tables for re- set# parameters and to figure 11 for the timing dia- gram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins (except for ry/by#) are placed in the highest impedance state table 5. secsi tm sector addresses sector size address range am29pdl127h/ am29pdl129h 128 words 000000h?00007fh factory-locked area 64 words 000000h-00003fh customer-lockable area 64 words 000040h-00007fh
november 24, 2003 am70pdl127cdh/am70pdl129cdh 19 advance information table 6. am29pdl127h sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 00000000000 4 000000h?000fffh sa1 00000000001 4 001000h?001fffh sa2 00000000010 4 002000h?002fffh sa3 00000000011 4 003000h?003fffh sa4 00000000100 4 004000h?004fffh sa5 00000000101 4 005000h?005fffh sa6 00000000110 4 006000h?006fffh sa7 00000000111 4 007000h?007fffh sa8 00000001xxx 32 008000h?00ffffh sa9 00000010xxx 32 010000h?017fffh sa10 00000011xxx 32 018000h?01ffffh sa11 00000100xxx 32 020000h?027fffh sa12 00000101xxx 32 028000h?02ffffh sa13 00000110xxx 32 030000h?037fffh sa14 00000111xxx 32 038000h?03ffffh sa15 00001000xxx 32 040000h?047fffh sa16 00001001xxx 32 048000h?04ffffh sa17 00001010xxx 32 050000h?057fffh sa18 00001011xxx 32 058000h?05ffffh sa19 00001100xxx 32 060000h?067fffh sa20 00001101xxx 32 068000h?06ffffh sa21 00001110xxx 32 070000h?077fffh sa22 00001111xxx 32 078000h?07ffffh sa23 00010000xxx 32 080000h?087fffh sa24 00010001xxx 32 088000h?08ffffh sa25 00010010xxx 32 090000h?097fffh sa26 00010011xxx 32 098000h?09ffffh sa27 00010100xxx 32 0a0000h?0a7fffh sa28 00010101xxx 32 0a8000h?0affffh sa29 00010110xxx 32 0b0000h?0b7fffh sa30 00010111xxx 32 0b8000h?0bffffh sa31 00011000xxx 32 0c0000h?0c7fffh sa32 00011001xxx 32 0c8000h?0cffffh sa33 00011010xxx 32 0d0000h?0d7fffh sa34 00011011xxx 32 0d8000h?0dffffh sa35 00011100xxx 32 0e0000h?0e7fffh sa36 00011101xxx 32 0e8000h?0effffh sa37 00011110xxx 32 0f0000h?0f7fffh sa38 00011111xxx 32 0f8000h?0fffffh
20 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank b sa39 00100000xxx 32 100000h?107fffh sa40 00100001xxx 32 108000h?10ffffh sa41 00100010xxx 32 110000h?117fffh sa42 00100011xxx 32 118000h?11ffffh sa43 00100100xxx 32 120000h?127fffh sa44 00100101xxx 32 128000h?12ffffh sa45 00100110xxx 32 130000h?137fffh sa46 00100111xxx 32 138000h?13ffffh sa47 00101000xxx 32 140000h?147fffh sa48 00101001xxx 32 148000h?14ffffh sa49 00101010xxx 32 150000h?157fffh sa50 00101011xxx 32 158000h?15ffffh sa51 00101100xxx 32 160000h?167fffh sa52 00101101xxx 32 168000h?16ffffh sa53 00101110xxx 32 170000h?177fffh sa54 00101111xxx 32 178000h?17ffffh sa55 00110000xxx 32 180000h?187fffh sa56 00110001xxx 32 188000h?18ffffh sa57 00110010xxx 32 190000h?197fffh sa58 00110011xxx 32 198000h?19ffffh sa59 00110100xxx 32 1a0000h?1a7fffh sa60 00110101xxx 32 1a8000h?1affffh sa61 00110110xxx 32 1b0000h?1b7fffh sa62 00110111xxx 32 1b8000h?1bffffh sa63 00111000xxx 32 1c0000h?1c7fffh sa64 00111001xxx 32 1c8000h?1cffffh sa65 00111010xxx 32 1d0000h?1d7fffh sa66 00111011xxx 32 1d8000h?1dffffh sa67 00111100xxx 32 1e0000h?1e7fffh sa68 00111101xxx 32 1e8000h?1effffh sa69 00111110xxx 32 1f0000h?1f7fffh sa70 00111111xxx 32 1f8000h?1fffffh sa71 01000000xxx 32 200000h?207fffh sa72 01000001xxx 32 208000h?20ffffh sa73 01000010xxx 32 210000h?217fffh sa74 01000011xxx 32 218000h?21ffffh sa75 01000100xxx 32 220000h?227fffh sa76 01000101xxx 32 228000h?22ffffh sa77 01000110xxx 32 230000h?237fffh sa78 01000111xxx 32 238000h?23ffffh table 6. am29pdl127h sector architecture (continued)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 21 advance information bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank b sa79 01001000xxx 32 240000h?247fffh sa80 01001001xxx 32 248000h?24ffffh sa81 01001010xxx 32 250000h?257fffh sa82 01001011xxx 32 258000h?25ffffh sa83 01001100xxx 32 260000h?267fffh sa84 01001101xxx 32 268000h?26ffffh sa85 01001110xxx 32 270000h?277fffh sa86 01001111xxx 32 278000h?27ffffh sa87 01010000xxx 32 280000h?287fffh sa88 01010001xxx 32 288000h?28ffffh sa89 01010010xxx 32 290000h?297fffh sa90 01010011xxx 32 298000h?29ffffh sa91 01010100xxx 32 2a0000h?2a7fffh sa92 01010101xxx 32 2a8000h?2affffh sa93 01010110xxx 32 2b0000h?2b7fffh sa94 01010111xxx 32 2b8000h?2bffffh sa95 01011000xxx 32 2c0000h?2c7fffh sa96 01011001xxx 32 2c8000h?2cffffh sa97 01011010xxx 32 2d0000h?2d7fffh sa98 01011011xxx 32 2d8000h?2dffffh sa99 01011100xxx 32 2e0000h?2e7fffh sa100 01011101xxx 32 2e8000h?2effffh sa101 01011110xxx 32 2f0000h?2f7fffh sa102 01011111xxx 32 2f8000h?2fffffh sa103 01100000xxx 32 300000h?307fffh sa104 01100001xxx 32 308000h?30ffffh sa105 01100010xxx 32 310000h?317fffh sa106 01100011xxx 32 318000h?31ffffh sa107 01100100xxx 32 320000h?327fffh sa108 01100101xxx 32 328000h?32ffffh sa109 01100110xxx 32 330000h?337fffh sa110 01100111xxx 32 338000h?33ffffh sa111 01101000xxx 32 340000h?347fffh sa112 01101001xxx 32 348000h?34ffffh sa113 01101010xxx 32 350000h?357fffh sa114 01101011xxx 32 358000h?35ffffh sa115 01101100xxx 32 360000h?367fffh sa116 01101101xxx 32 368000h?36ffffh sa117 01101110xxx 32 370000h?377fffh sa118 01101111xxx 32 378000h?37ffffh table 6. am29pdl127h sector architecture (continued)
22 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank b sa119 01110000xxx 32 380000h?387fffh sa120 01110001xxx 32 388000h?38ffffh sa121 01110010xxx 32 390000h?397fffh sa122 01110011xxx 32 398000h?39ffffh sa123 01110100xxx 32 3a0000h?3a7fffh sa124 01110101xxx 32 3a8000h?3affffh sa125 01110110xxx 32 3b0000h?3b7fffh sa126 01110111xxx 32 3b8000h?3bffffh sa127 01111000xxx 32 3c0000h?3c7fffh sa128 01111001xxx 32 3c8000h?3cffffh sa129 01111010xxx 32 3d0000h?3d7fffh sa130 01111011xxx 32 3d8000h?3dffffh sa131 01111100xxx 32 3e0000h?3e7fffh sa132 01111101xxx 32 3e8000h?3effffh sa133 01111110xxx 32 3f0000h?3f7fffh sa134 01111111xxx 32 3f8000h?3fffffh bank c sa135 10000000xxx 32 400000h?407fffh sa136 10000001xxx 32 408000h?40ffffh sa137 10000010xxx 32 410000h?417fffh sa138 10000011xxx 32 418000h?41ffffh sa139 10000100xxx 32 420000h?427fffh sa140 10000101xxx 32 428000h?42ffffh sa141 10000110xxx 32 430000h?437fffh sa142 10000111xxx 32 438000h?43ffffh sa143 10001000xxx 32 440000h?447fffh sa144 10001001xxx 32 448000h?44ffffh sa145 10001010xxx 32 450000h?457fffh sa146 10001011xxx 32 458000h?45ffffh sa147 10001100xxx 32 460000h?467fffh sa148 10001101xxx 32 468000h?46ffffh sa149 10001110xxx 32 470000h?477fffh sa150 10001111xxx 32 478000h?47ffffh sa151 10010000xxx 32 480000h?487fffh sa152 10010001xxx 32 488000h?48ffffh sa153 10010010xxx 32 490000h?497fffh sa154 10010011xxx 32 498000h?49ffffh sa155 10010100xxx 32 4a0000h?4a7fffh sa156 10010101xxx 32 4a8000h?4affffh sa157 10010110xxx 32 4b0000h?4b7fffh sa158 10010111xxx 32 4b8000h?4bffffh table 6. am29pdl127h sector architecture (continued)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 23 advance information bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank c sa159 10011000xxx 32 4c0000h?4c7fffh sa160 10011001xxx 32 4c8000h?4cffffh sa161 10011010xxx 32 4d0000h?4d7fffh sa162 10011011xxx 32 4d8000h?4dffffh sa163 10011100xxx 32 4e0000h?4e7fffh sa164 10011101xxx 32 4e8000h?4effffh sa165 10011110xxx 32 4f0000h?4f7fffh sa166 10011111xxx 32 4f8000h?4fffffh sa167 10100000xxx 32 500000h?507fffh sa168 10100001xxx 32 508000h?50ffffh sa169 10100010xxx 32 510000h?517fffh sa170 10100011xxx 32 518000h?51ffffh sa171 10100100xxx 32 520000h?527fffh sa172 10100101xxx 32 528000h?52ffffh sa173 10100110xxx 32 530000h?537fffh sa174 10100111xxx 32 538000h?53ffffh sa175 10101000xxx 32 540000h?547fffh sa176 10101001xxx 32 548000h?54ffffh sa177 10101010xxx 32 550000h?557fffh sa178 10101011xxx 32 558000h?15ffffh sa179 10101100xxx 32 560000h?567fffh sa180 10101101xxx 32 568000h?56ffffh sa181 10101110xxx 32 570000h?577fffh sa182 10101111xxx 32 578000h?57ffffh sa183 10110000xxx 32 580000h?587fffh sa184 10110001xxx 32 588000h?58ffffh sa185 10110010xxx 32 590000h?597fffh sa186 10110011xxx 32 598000h?59ffffh sa187 10110100xxx 32 5a0000h?5a7fffh sa188 10110101xxx 32 5a8000h?5affffh sa189 10110110xxx 32 5b0000h?5b7fffh sa190 10110111xxx 32 5b8000h?5bffffh sa191 10111000xxx 32 5c0000h?5c7fffh sa192 10111001xxx 32 5c8000h?5cffffh sa193 10111010xxx 32 5d0000h?5d7fffh sa194 10111011xxx 32 5d8000h?5dffffh sa195 10111100xxx 32 5e0000h?5e7fffh sa196 10111101xxx 32 5e8000h?5effffh sa197 10111110xxx 32 5f0000h?5f7fffh sa198 10111111xxx 32 5f8000h?5fffffh table 6. am29pdl127h sector architecture (continued)
24 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank c sa199 11000000xxx 32 600000h?607fffh sa200 11000001xxx 32 608000h?60ffffh sa201 11000010xxx 32 610000h?617fffh sa202 11000011xxx 32 618000h?61ffffh sa203 11000100xxx 32 620000h?627fffh sa204 11000101xxx 32 628000h?62ffffh sa205 11000110xxx 32 630000h?637fffh sa206 11000111xxx 32 638000h?63ffffh sa207 11001000xxx 32 640000h?647fffh sa208 11001001xxx 32 648000h?64ffffh sa209 11001010xxx 32 650000h?657fffh sa210 11001011xxx 32 658000h?65ffffh sa211 11001100xxx 32 660000h?667fffh sa212 11001101xxx 32 668000h?66ffffh sa213 11001110xxx 32 670000h?677fffh sa214 11001111xxx 32 678000h?67ffffh sa215 11010000xxx 32 680000h?687fffh sa216 11010001xxx 32 688000h?68ffffh sa217 11010010xxx 32 690000h?697fffh sa218 11010011xxx 32 698000h?69ffffh sa219 11010100xxx 32 6a0000h?6a7fffh sa220 11010101xxx 32 6a8000h?6affffh sa221 11010110xxx 32 6b0000h?6b7fffh sa222 11010111xxx 32 6b8000h?6bffffh sa223 11011000xxx 32 6c0000h?6c7fffh sa224 11011001xxx 32 6c8000h?6cffffh sa225 11011010xxx 32 6d0000h?6d7fffh sa226 11011011xxx 32 6d8000h?6dffffh sa227 11011100xxx 32 6e0000h?6e7fffh sa228 11011101xxx 32 6e8000h?6effffh sa229 11011110xxx 32 6f0000h?6f7fffh sa230 11011111xxx 32 6f8000h?6fffffh table 6. am29pdl127h sector architecture (continued)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 25 advance information bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank d sa231 11100000xxx 32 700000h?707fffh sa232 11100001xxx 32 708000h?70ffffh sa233 11100010xxx 32 710000h?717fffh sa234 11100011xxx 32 718000h?71ffffh sa235 11100100xxx 32 720000h?727fffh sa236 11100101xxx 32 728000h?72ffffh sa237 11100110xxx 32 730000h?737fffh sa238 11100111xxx 32 738000h?73ffffh sa239 11101000xxx 32 740000h?747fffh sa240 11101001xxx 32 748000h?74ffffh sa241 11101010xxx 32 750000h?757fffh sa242 11101011xxx 32 758000h?75ffffh sa243 11101100xxx 32 760000h?767fffh sa244 11101101xxx 32 768000h?76ffffh sa245 11101110xxx 32 770000h?777fffh sa246 11101111xxx 32 778000h?77ffffh sa247 11110000xxx 32 780000h?787fffh sa248 11110001xxx 32 788000h?78ffffh sa249 11110010xxx 32 790000h?797fffh sa250 11110011xxx 32 798000h?79ffffh sa251 11110100xxx 32 7a0000h?7a7fffh sa252 11110101xxx 32 7a8000h?7affffh sa253 11110110xxx 32 7b0000h?7b7fffh sa254 11110111xxx 32 7b8000h?7bffffh sa255 11111000xxx 32 7c0000h?7c7fffh sa256 11111001xxx 32 7c8000h?7cffffh sa257 11111010xxx 32 7d0000h?7d7fffh sa258 11111011xxx 32 7d8000h?7dffffh sa259 11111100xxx 32 7e0000h?7e7fffh sa260 11111101xxx 32 7e8000h?7effffh sa261 11111110xxx 32 7f0000h?7f7fffh sa262 11111111000 4 7f8000h?7f8fffh sa263 11111111001 4 7f9000h?7f9fffh sa264 11111111010 4 7fa000h?7fafffh sa265 11111111011 4 7fb000h?7fbfffh sa266 11111111100 4 7fc000h?7fcfffh sa267 11111111101 4 7fd000h?7fdfffh sa268 11111111110 4 7fe000h?7fefffh sa269 11111111111 4 7ff000h?7fffffh table 6. am29pdl127h sector architecture (continued)
26 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information table 7. am29pdl129h sector architecture bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) bank 1a sa1-0 0 1 0000000xxx 32 000000h?007fffh sa1-1 0 1 0000001xxx 32 008000h?00ffffh sa1-2 0 1 0000010xxx 32 010000h?017fffh sa1-3 0 1 0000011xxx 32 018000h?01ffffh sa1-4 0 1 0000100xxx 32 020000h?027fffh sa1-5 0 1 0000101xxx 32 028000h?02ffffh sa1-6 0 1 0000110xxx 32 030000h?037fffh sa1-7 0 1 0000111xxx 32 038000h?03ffffh sa1-8 0 1 0001000xxx 32 040000h?047fffh sa1-9 0 1 0001001xxx 32 048000h?04ffffh sa1-10 0 1 0001010xxx 32 050000h?057fffh sa1-11 0 1 0001011xxx 32 058000h?05ffffh sa1-12 0 1 0001100xxx 32 060000h?067fffh sa1-13 0 1 0001101xxx 32 068000h?06ffffh sa1-14 0 1 0001110xxx 32 070000h?077fffh sa1-15 0 1 0001111xxx 32 078000h?07ffffh sa1-16 0 1 0010000xxx 32 080000h?087fffh sa1-17 0 1 0010001xxx 32 088000h?08ffffh sa1-18 0 1 0010010xxx 32 090000h?097fffh sa1-19 0 1 0010011xxx 32 098000h?09ffffh sa1-20 0 1 0010100xxx 32 0a0000h?0a7fffh sa1-21 0 1 0010101xxx 32 0a8000h?0affffh sa1-22 0 1 0010110xxx 32 0b0000h?0b7fffh sa1-23 0 1 0010111xxx 32 0b8000h?0bffffh sa1-24 0 1 0011000xxx 32 0c0000h?0c7fffh sa1-25 0 1 0011001xxx 32 0c8000h?0cffffh sa1-26 0 1 0011010xxx 32 0d0000h?0d7fffh sa1-27 0 1 0011011xxx 32 0d8000h?0dffffh sa1-28 0 1 0011100xxx 32 0e0000h?0e7fffh sa1-29 0 1 0011101xxx 32 0e8000h?0effffh sa1-30 0 1 0011110xxx 32 0f0000h?0f7fffh sa1-31 0 1 0011111xxx 32 0f8000h?0fffffh sa1-32 0 1 0100000xxx 32 100000h?107fffh sa1-33 0 1 0100001xxx 32 108000h?10ffffh sa1-34 0 1 0100010xxx 32 110000h?117fffh sa1-35 0 1 0100011xxx 32 118000h?11ffffh sa1-36 0 1 0100100xxx 32 120000h?127fffh sa1-37 0 1 0100101xxx 32 128000h?12ffffh
november 24, 2003 am70pdl127cdh/am70pdl129cdh 27 advance information bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) bank 1a sa1-38 0 1 0100110xxx 32 130000h?137fffh sa1-39 0 1 0100111xxx 32 138000h?13ffffh sa1-40 0 1 0101000xxx 32 140000h?147fffh sa1-41 0 1 0101001xxx 32 148000h?14ffffh sa1-42 0 1 0101010xxx 32 150000h?157fffh sa1-43 0 1 0101011xxx 32 158000h?15ffffh sa1-44 0 1 0101100xxx 32 160000h?167fffh sa1-45 0 1 0101101xxx 32 168000h?16ffffh sa1-46 0 1 0101110xxx 32 170000h?177fffh sa1-47 0 1 0101111xxx 32 178000h?17ffffh sa1-48 0 1 0110000xxx 32 180000h?187fffh sa1-49 0 1 0110001xxx 32 188000h?18ffffh sa1-50 0 1 0110010xxx 32 190000h?197fffh sa1-51 0 1 0110011xxx 32 198000h?19ffffh sa1-52 0 1 0110100xxx 32 1a0000h?1a7fffh sa1-53 0 1 0110101xxx 32 1a8000h?1affffh sa1-54 0 1 0110110xxx 32 1b0000h?1b7fffh sa1-55 0 1 0110111xxx 32 1b8000h?1bffffh sa1-56 0 1 0111000xxx 32 1c0000h?1c7fffh sa1-57 0 1 0111001xxx 32 1c8000h?1cffffh sa1-58 0 1 0111010xxx 32 1d0000h?1d7fffh sa1-59 0 1 0111011xxx 32 1d8000h?1dffffh sa1-60 0 1 0111100xxx 32 1e0000h?1e7fffh sa1-61 0 1 0111101xxx 32 1e8000h?1effffh sa1-62 0 1 0111110xxx 32 1f0000h?1f7fffh sa1-63 0 1 0111111xxx 32 1f8000h?1fffffh sa1-64 0 1 1000000xxx 32 200000h?207fffh sa1-65 0 1 1000001xxx 32 208000h?20ffffh sa1-66 0 1 1000010xxx 32 210000h?217fffh sa1-67 0 1 1000011xxx 32 218000h?21ffffh sa1-68 0 1 1000100xxx 32 220000h?227fffh sa1-69 0 1 1000101xxx 32 228000h?22ffffh sa1-70 0 1 1000110xxx 32 230000h?237fffh sa1-71 0 1 1000111xxx 32 238000h?23ffffh sa1-72 0 1 1001000xxx 32 240000h?247fffh sa1-73 0 1 1001001xxx 32 248000h?24ffffh sa1-74 0 1 1001010xxx 32 250000h?257fffh sa1-75 0 1 1001011xxx 32 258000h?25ffffh sa1-76 0 1 1001100xxx 32 260000h?267fffh sa1-77 0 1 1001101xxx 32 268000h?26ffffh table 7. am29pdl129h sector architecture (continued)
28 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) bank 1a sa1-78 0 1 1001110xxx 32 270000h?277fffh sa1-79 0 1 1001111xxx 32 278000h?27ffffh sa1-80 0 1 1010000xxx 32 280000h?287fffh sa1-81 0 1 1010001xxx 32 288000h?28ffffh sa1-82 0 1 1010010xxx 32 290000h?297fffh sa1-83 0 1 1010011xxx 32 298000h?29ffffh sa1-84 0 1 1010100xxx 32 2a0000h?2a7fffh sa1-85 0 1 1010101xxx 32 2a8000h?2affffh sa1-86 0 1 1010110xxx 32 2b0000h?2b7fffh sa1-87 0 1 1010111xxx 32 2b8000h?2bffffh sa1-88 0 1 1011000xxx 32 2c0000h?2c7fffh sa1-89 0 1 1011001xxx 32 2c8000h?2cffffh sa1-90 0 1 1011010xxx 32 2d0000h?2d7fffh sa1-91 0 1 1011011xxx 32 2d8000h?2dffffh sa1-92 0 1 1011100xxx 32 2e0000h?2e7fffh sa1-93 0 1 1011101xxx 32 2e8000h?2effffh sa1-94 0 1 1011110xxx 32 2f0000h?2f7fffh sa1-95 0 1 1011111xxx 32 2f8000h?2fffffh table 7. am29pdl129h sector architecture (continued)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 29 advance information bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) bank 1b sa1-96 0 1 1100000xxx 32 300000h?307fffh sa1-97 0 1 1100001xxx 32 308000h?30ffffh sa1-98 0 1 1100010xxx 32 310000h?317fffh sa1-99 0 1 1100011xxx 32 318000h?31ffffh sa1-100 0 1 1100100xxx 32 320000h?327fffh sa1-101 0 1 1100101xxx 32 328000h?32ffffh sa1-102 0 1 1100110xxx 32 330000h?337fffh sa1-103 0 1 1100111xxx 32 338000h?33ffffh sa1-104 0 1 1101000xxx 32 340000h?347fffh sa1-105 0 1 1101001xxx 32 348000h?34ffffh sa1-106 0 1 1101010xxx 32 350000h?357fffh sa1-107 0 1 1101011xxx 32 358000h?35ffffh sa1-108 0 1 1101100xxx 32 360000h?367fffh sa1-109 0 1 1101101xxx 32 368000h?36ffffh sa1-110 0 1 1101110xxx 32 370000h?377fffh sa1-111 0 1 1101111xxx 32 378000h?37ffffh sa1-112 0 1 1110000xxx 32 380000h?387fffh sa1-113 0 1 1110001xxx 32 388000h?38ffffh sa1-114 0 1 1110010xxx 32 390000h?397fffh sa1-115 0 1 1110011xxx 32 398000h?39ffffh sa1-116 0 1 1110100xxx 32 3a0000h?3a7fffh sa1-117 0 1 1110101xxx 32 3a8000h?3affffh sa1-118 0 1 1110110xxx 32 3b0000h?3b7fffh sa1-119 0 1 1110111xxx 32 3b8000h?3bffffh sa1-120 0 1 1111000xxx 32 3c0000h?3c7fffh sa1-121 0 1 1111001xxx 32 3c8000h?3cffffh sa1-122 0 1 1111010xxx 32 3d0000h?3d7fffh sa1-123 0 1 1111011xxx 32 3d8000h?3dffffh sa1-124 0 1 1111100xxx 32 3e0000h?3e7fffh sa1-125 0 1 1111101xxx 32 3e8000h?3effffh sa1-126 0 1 1111110xxx 32 3f0000h?3f7fffh sa1-127 0 1 1111111000 4 3f8000h?3f8fffh sa1-128 0 1 1111111001 4 3f9000h?3f9fffh sa1-129 0 1 1111111010 4 3fa000h?3fafffh sa1-130 0 1 1111111011 4 3fb000h?3fbfffh sa1-131 0 1 1111111100 4 3fc000h?3fcfffh sa1-132 0 1 1111111101 4 3fd000h?3fdfffh sa1-133 0 1 1111111110 4 3fe000h?3fefffh sa1-134 0 1 1111111111 4 3ff000h?3fffffh table 7. am29pdl129h sector architecture (continued)
30 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) bank 2a sa2-0 1 0 0000000000 4 000000h?000fffh sa2-1 1 0 0000000001 4 001000h?001fffh sa2-2 1 0 0000000010 4 002000h?002fffh sa2-3 1 0 0000000011 4 003000h?003fffh sa2-4 1 0 0000000100 4 004000h?004fffh sa2-5 1 0 0000000101 4 005000h?005fffh sa2-6 1 0 0000000110 4 006000h?006fffh sa2-7 1 0 0000000111 4 007000h?007fffh sa2-8 1 0 0000001xxx 32 008000h?00ffffh sa2-9 1 0 0000010xxx 32 010000h?017fffh sa2-10 1 0 0000011xxx 32 018000h?01ffffh sa2-11 1 0 0000100xxx 32 020000h?027fffh sa2-12 1 0 0000101xxx 32 028000h?02ffffh sa2-13 1 0 0000110xxx 32 030000h?037fffh sa2-14 1 0 0000111xxx 32 038000h?03ffffh sa2-15 1 0 0001000xxx 32 040000h?047fffh sa2-16 1 0 0001001xxx 32 048000h?04ffffh sa2-17 1 0 0001010xxx 32 050000h?057fffh sa2-18 1 0 0001011xxx 32 058000h?05ffffh sa2-19 1 0 0001100xxx 32 060000h?067fffh sa2-20 1 0 0001101xxx 32 068000h?06ffffh sa2-21 1 0 0001110xxx 32 070000h?077fffh sa2-22 1 0 0001111xxx 32 078000h?07ffffh sa2-23 1 0 0010000xxx 32 080000h?087fffh sa2-24 1 0 0010001xxx 32 088000h?08ffffh sa2-25 1 0 0010010xxx 32 090000h?097fffh sa2-26 1 0 0010011xxx 32 098000h?09ffffh sa2-27 1 0 0010100xxx 32 0a0000h?0a7fffh sa2-28 1 0 0010101xxx 32 0a8000h?0affffh sa2-29 1 0 0010110xxx 32 0b0000h?0b7fffh sa2-30 1 0 0010111xxx 32 0b8000h?0bffffh sa2-31 1 0 0011000xxx 32 0c0000h?0c7fffh sa2-32 1 0 0011001xxx 32 0c8000h?0cffffh sa2-33 1 0 0011010xxx 32 0d0000h?0d7fffh sa2-34 1 0 0011011xxx 32 0d8000h?0dffffh sa2-35 1 0 0011100xxx 32 0e0000h?0e7fffh sa2-36 1 0 0011101xxx 32 0e8000h?0effffh sa2-37 1 0 0011110xxx 32 0f0000h?0f7fffh sa2-38 1 0 0011111xxx 32 0f8000h?0fffffh table 7. am29pdl129h sector architecture (continued)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 31 advance information bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) bank 2b sa2-39 1 0 0100000xxx 32 100000h?107fffh sa2-40 1 0 0100001xxx 32 108000h?10ffffh sa2-41 1 0 0100010xxx 32 110000h?117fffh sa2-42 1 0 0100011xxx 32 118000h?11ffffh sa2-43 1 0 0100100xxx 32 120000h?127fffh sa2-44 1 0 0100101xxx 32 128000h?12ffffh sa2-45 1 0 0100110xxx 32 130000h?137fffh sa2-46 1 0 0100111xxx 32 138000h?13ffffh sa2-47 1 0 0101000xxx 32 140000h?147fffh sa2-48 1 0 0101001xxx 32 148000h?14ffffh sa2-49 1 0 0101010xxx 32 150000h?157fffh sa2-50 1 0 0101011xxx 32 158000h?15ffffh sa2-51 1 0 0101100xxx 32 160000h?167fffh sa2-52 1 0 0101101xxx 32 168000h?16ffffh sa2-53 1 0 0101110xxx 32 170000h?177fffh sa2-54 1 0 0101111xxx 32 178000h?17ffffh sa2-55 1 0 0110000xxx 32 180000h?187fffh sa2-56 1 0 0110001xxx 32 188000h?18ffffh sa2-57 1 0 0110010xxx 32 190000h?197fffh sa2-58 1 0 0110011xxx 32 198000h?19ffffh sa2-59 1 0 0110100xxx 32 1a0000h?1a7fffh sa2-60 1 0 0110101xxx 32 1a8000h?1affffh sa2-61 1 0 0110110xxx 32 1b0000h?1b7fffh sa2-62 1 0 0110111xxx 32 1b8000h?1bffffh sa2-63 1 0 0111000xxx 32 1c0000h?1c7fffh sa2-64 1 0 0111001xxx 32 1c8000h?1cffffh sa2-65 1 0 0111010xxx 32 1d0000h?1d7fffh sa2-66 1 0 0111011xxx 32 1d8000h?1dffffh sa2-67 1 0 0111100xxx 32 1e0000h?1e7fffh sa2-68 1 0 0111101xxx 32 1e8000h?1effffh sa2-69 1 0 0111110xxx 32 1f0000h?1f7fffh sa2-70 1 0 0111111xxx 32 1f8000h?1fffffh sa2-71 1 0 1000000xxx 32 200000h?207fffh sa2-72 1 0 1000001xxx 32 208000h?20ffffh sa2-73 1 0 1000010xxx 32 210000h?217fffh sa2-74 1 0 1000011xxx 32 218000h?21ffffh sa2-75 1 0 1000100xxx 32 220000h?227fffh sa2-76 1 0 1000101xxx 32 228000h?22ffffh sa2-77 1 0 1000110xxx 32 230000h?237fffh sa2-78 1 0 1000111xxx 32 238000h?23ffffh table 7. am29pdl129h sector architecture (continued)
32 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) bank 2b sa2-79 1 0 1001000xxx 32 240000h?247fffh sa2-80 1 0 1001001xxx 32 248000h?24ffffh sa2-81 1 0 1001010xxx 32 250000h?257fffh sa2-82 1 0 1001011xxx 32 258000h?25ffffh sa2-83 1 0 1001100xxx 32 260000h?267fffh sa2-84 1 0 1001101xxx 32 268000h?26ffffh sa2-85 1 0 1001110xxx 32 270000h?277fffh sa2-86 1 0 1001111xxx 32 278000h?27ffffh sa2-87 1 0 1010000xxx 32 280000h?287fffh sa2-88 1 0 1010001xxx 32 288000h?28ffffh sa2-89 1 0 1010010xxx 32 290000h?297fffh sa2-90 1 0 1010011xxx 32 298000h?29ffffh sa2-91 1 0 1010100xxx 32 2a0000h?2a7fffh sa2-92 1 0 1010101xxx 32 2a8000h?2affffh sa2-93 1 0 1010110xxx 32 2b0000h?2b7fffh sa2-94 1 0 1010111xxx 32 2b8000h?2bffffh sa2-95 1 0 1011000xxx 32 2c0000h?2c7fffh sa2-96 1 0 1011001xxx 32 2c8000h?2cffffh sa2-97 1 0 1011010xxx 32 2d0000h?2d7fffh sa2-98 1 0 1011011xxx 32 2d8000h?2dffffh sa2-99 1 0 1011100xxx 32 2e0000h?2e7fffh sa2-100 1 0 1011101xxx 32 2e8000h?2effffh sa2-101 1 0 1011110xxx 32 2f0000h?2f7fffh sa2-102 1 0 1011111xxx 32 2f8000h?2fffffh sa2-103 1 0 1100000xxx 32 300000h?307fffh sa2-104 1 0 1100001xxx 32 308000h?30ffffh sa2-105 1 0 1100010xxx 32 310000h?317fffh sa2-106 1 0 1100011xxx 32 318000h?31ffffh sa2-107 1 0 1100100xxx 32 320000h?327fffh sa2-108 1 0 1100101xxx 32 328000h?32ffffh sa2-109 1 0 1100110xxx 32 330000h?337fffh sa2-110 1 0 1100111xxx 32 338000h?33ffffh sa2-111 1 0 1101000xxx 32 340000h?347fffh sa2-112 1 0 1101001xxx 32 348000h?34ffffh sa2-113 1 0 1101010xxx 32 350000h?357fffh sa2-114 1 0 1101011xxx 32 358000h?35ffffh sa2-115 1 0 1101100xxx 32 360000h?367fffh sa2-116 1 0 1101101xxx 32 368000h?36ffffh sa2-117 1 0 1101110xxx 32 370000h?377fffh sa2-118 1 0 1101111xxx 32 378000h?37ffffh table 7. am29pdl129h sector architecture (continued)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 33 advance information bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) bank 2b sa2-119 1 0 1110000xxx 32 380000h?387fffh sa2-120 1 0 1110001xxx 32 388000h?38ffffh sa2-121 1 0 1110010xxx 32 390000h?397fffh sa2-122 1 0 1110011xxx 32 398000h?39ffffh sa2-123 1 0 1110100xxx 32 3a0000h?3a7fffh sa2-124 1 0 1110101xxx 32 3a8000h?3affffh sa2-125 1 0 1110110xxx 32 3b0000h?3b7fffh sa2-126 1 0 1110111xxx 32 3b8000h?3bffffh sa2-127 1 0 1111000xxx 32 3c0000h?3c7fffh sa2-128 1 0 1111001xxx 32 3c8000h?3cffffh sa2-129 1 0 1111010xxx 32 3d0000h?3d7fffh sa2-130 1 0 1111011xxx 32 3d8000h?3dffffh sa2-131 1 0 1111100xxx 32 3e0000h?3e7fffh sa2-132 1 0 1111101xxx 32 3e8000h?3effffh sa2-133 1 0 1111110xxx 32 3f0000h?3f7fffh sa2-134 1 0 1111111xxx 32 3f8000h?3fffffh table 7. am29pdl129h sector architecture (continued)
34 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information table 8. am29pdl127h boot sector/sector block addresses for protection/unprotection sector a22-a12 sector/ sector block size sa0 00000000000 4 kwords sa1 00000000001 4 kwords sa2 00000000010 4 kwords sa3 00000000011 4 kwords sa4 00000000100 4 kwords sa5 00000000101 4 kwords sa6 00000000110 4 kwords sa7 00000000111 4 kwords sa8 00000001xxx 32 kwords sa9 00000010xxx 32 kwords sa10 00000011xxx 32 kwords sa11-sa14 000001xxxxx 128 (4x32) kwords sa15-sa18 000010xxxxx 128 (4x32) kwords sa19-sa22 000011xxxxx 128 (4x32) kwords sa23-sa26 000100xxxxx 128 (4x32) kwords sa27-sa30 000101xxxxx 128 (4x32) kwords sa31-sa34 000110xxxxx 128 (4x32) kwords sa35-sa38 000111xxxxx 128 (4x32) kwords sa39-sa42 001000xxxxx 128 (4x32) kwords sa43-sa46 001001xxxxx 128 (4x32) kwords sa47-sa50 001010xxxxx 128 (4x32) kwords sa51-sa54 001011xxxxx 128 (4x32) kwords sa55-sa58 001100xxxxx 128 (4x32) kwords sa59-sa62 001101xxxxx 128 (4x32) kwords sa63-sa66 001110xxxxx 128 (4x32) kwords sa67-sa70 001111xxxxx 128 (4x32) kwords sa71-sa74 010000xxxxx 128 (4x32) kwords sa75-sa78 010001xxxxx 128 (4x32) kwords sa79-sa82 010010xxxxx 128 (4x32) kwords sa83-sa86 010011xxxxx 128 (4x32) kwords sa87-sa90 010100xxxxx 128 (4x32) kwords sa91-sa94 010101xxxxx 128 (4x32) kwords sa95-sa98 010110xxxxx 128 (4x32) kwords sa99-sa102 010111xxxxx 128 (4x32) kwords sa103-sa106 011000xxxxx 128 (4x32) kwords sa107-sa110 011001xxxxx 128 (4x32) kwords sa111-sa114 011010xxxxx 128 (4x32) kwords sa115-sa118 011011xxxxx 128 (4x32) kwords sa119-sa122 011100xxxxx 128 (4x32) kwords sa123-sa126 011101xxxxx 128 (4x32) kwords sa127-sa130 011110xxxxx 128 (4x32) kwords sector a22-a12 sector/ sector block size sa131-sa134 011111xxxxx 128 (4x32) kwords sa135-sa138 100000xxxxx 128 (4x32) kwords sa139-sa142 100001xxxxx 128 (4x32) kwords sa143-sa146 100010xxxxx 128 (4x32) kwords sa147-sa150 100011xxxxx 128 (4x32) kwords sa151-sa154 100100xxxxx 128 (4x32) kwords sa155-sa158 100101xxxxx 128 (4x32) kwords sa159-sa162 100110xxxxx 128 (4x32) kwords sa163-sa166 100111xxxxx 128 (4x32) kwords sa167-sa170 101000xxxxx 128 (4x32) kwords sa171-sa174 101001xxxxx 128 (4x32) kwords sa175-sa178 101010xxxxx 128 (4x32) kwords sa179-sa182 101011xxxxx 128 (4x32) kwords sa183-sa186 101100xxxxx 128 (4x32) kwords sa187-sa190 101101xxxxx 128 (4x32) kwords sa191-sa194 101110xxxxx 128 (4x32) kwords sa195-sa198 101111xxxxx 128 (4x32) kwords sa199-sa202 110000xxxxx 128 (4x32) kwords sa203-sa206 110001xxxxx 128 (4x32) kwords sa207-sa210 110010xxxxx 128 (4x32) kwords sa211-sa214 110011xxxxx 128 (4x32) kwords sa215-sa218 110100xxxxx 128 (4x32) kwords sa219-sa222 110101xxxxx 128 (4x32) kwords sa223-sa226 110110xxxxx 128 (4x32) kwords sa227-sa230 110111xxxxx 128 (4x32) kwords sa231-sa234 111000xxxxx 128 (4x32) kwords sa235-sa238 111001xxxxx 128 (4x32) kwords sa239-sa242 111010xxxxx 128 (4x32) kwords sa243-sa246 111011xxxxx 128 (4x32) kwords sa247-sa250 111100xxxxx 128 (4x32) kwords sa251-sa254 111101xxxxx 128 (4x32) kwords sa255-sa258 111110xxxxx 128 (4x32) kwords sa259 11111100xxx 32 kwords sa260 11111101xxx 32 kwords sa261 11111110xxx 32 kwords sa262 11111111000 4 kwords sa263 11111111001 4 kwords sa264 11111111010 4 kwords sa265 11111111011 4 kwords sa266 11111111100 4 kwords sa267 11111111101 4 kwords sa268 11111111110 4 kwords sa269 11111111111 4 kwords
november 24, 2003 am70pdl127cdh/am70pdl129cdh 35 advance information table 9. am29pdl129h boot sector/sector block addresses for protection/unprotection ce#f1 control table 10. am29pdl129h boot sector/sector block addresses for protection/unprotection ce#f2 control sector group a21-12 sector/sector block size sa1-0?sa1-3 00000xxxxx 128 (4x32) kwords sa1-4?sa1-7 00001xxxxx 128 (4x32) kwords sa1-8?sa1-11 00010xxxxx 128 (4x32) kwords sa1-12?sa1-15 00011xxxxx 128 (4x32) kwords sa1-16?sa1-19 00100xxxxx 128 (4x32) kwords sa1-20?sa1-23 00101xxxxx 128 (4x32) kwords sa1-24?sa1-27 00110xxxxx 128 (4x32) kwords sa1-28?sa1-31 00111xxxxx 128 (4x32) kwords sa1-32?sa1-35 01000xxxxx 128 (4x32) kwords sa1-36?sa1-39 01001xxxxx 128 (4x32) kwords sa1-40?sa1-43 01010xxxxx 128 (4x32) kwords sa1-44?sa1-47 01011xxxxx 128 (4x32) kwords sa1-48?sa1-51 01100xxxxx 128 (4x32) kwords sa1-52?sa1-55 01101xxxxx 128 (4x32) kwords sa1-56?sa1-59 01110xxxxx 128 (4x32) kwords sa1-60?sa1-63 01111xxxxx 128 (4x32) kwords sa1-64?sa1-67 10000xxxxx 128 (4x32) kwords sa1-68?sa1-71 10001xxxxx 128 (4x32) kwords sa1-72?sa1-75 10010xxxxx 128 (4x32) kwords sa1-76?sa1-79 10011xxxxx 128 (4x32) kwords sa1-80?sa1-83 10100xxxxx 128 (4x32) kwords sa1-84?sa1-87 10101xxxxx 128 (4x32) kwords sa1-88?sa1-91 10110xxxxx 128 (4x32) kwords sa1-92?sa1-95 10111xxxxx 128 (4x32) kwords sa1-96?sa1-99 11000xxxxx 128 (4x32) kwords sa1-100?sa1-103 11001xxxxx 128 (4x32) kwords sa1-104?sa1-107 11010xxxxx 128 (4x32) kwords sa1-108?sa1-111 11011xxxxx 128 (4x32) kwords sa1-112?sa1-115 11100xxxxx 128 (4x32) kwords sa1-116?sa1-119 11101xxxxx 128 (4x32) kwords sa1-120?sa1-123 11110xxxxx 128 (4x32) kwords sa1-124 1111100xxx 32 kwords sa1-125 1111101xxx 32 kwords sa1-126 1111110xxx 32 kwords sa1-127 1111111000 4 kwords sa1-128 1111111001 4 kwords sa1-129 1111111010 4 kwords sa1-130 1111111011 4 kwords sa1-131 1111111100 4 kwords sa1-132 1111111101 4 kwords sa1-133 1111111110 4 kwords sa1-134 1111111111 4 kwords sector group a21-12 sector/sector block size sa2-0 0000000000 4 kwords sa2-1 0000000001 4 kwords sa2-2 0000000010 4 kwords sa2-3 0000000011 4 kwords sa2-4 0000000100 4 kwords sa2-5 0000000101 4 kwords sa2-6 0000000110 4 kwords sa2-7 0000000111 4 kwords sa2-8 0000001xxx 32 kwords sa2-9 0000010xxx 32 kwords sa2-10 0000011xxx 32 kwords sa2-11 - sa2-14 00001xxxxx 128 (4x32) kwords sa2-15 - sa2-18 00010xxxxx 128 (4x32) kwords sa2-19 - sa2-22 00011xxxxx 128 (4x32) kwords sa2-23 - sa2-26 00100xxxxx 128 (4x32) kwords sa2-27 - sa2-30 00101xxxxx 128 (4x32) kwords sa2-31 - sa2-34 00110xxxxx 128 (4x32) kwords sa2-35 - sa2-38 00111xxxxx 128 (4x32) kwords sa2-39 - sa2-42 01000xxxxx 128 (4x32) kwords sa2-43 - sa2-46 01001xxxxx 128 (4x32) kwords sa2-47 - sa2-50 01010xxxxx 128 (4x32) kwords sa2-51 - sa2-54 01011xxxxx 128 (4x32) kwords sa2-55 - sa2-58 01100xxxxx 128 (4x32) kwords sa2-59 - sa2-62 01101xxxxx 128 (4x32) kwords sa2-63 - sa2-66 01110xxxxx 128 (4x32) kwords sa2-67 - sa2-70 01111xxxxx 128 (4x32) kwords sa2-71 - sa2-74 10000xxxxx 128 (4x32) kwords sa2-75 - sa2-78 10001xxxxx 128 (4x32) kwords sa2-79 - sa2-82 10010xxxxx 128 (4x32) kwords sa2-83 - sa2-86 10011xxxxx 128 (4x32) kwords sa2-87 - sa2-90 10100xxxxx 128 (4x32) kwords sa2-91 - sa2-94 10101xxxxx 128 (4x32) kwords sa2-95 - sa2-98 10110xxxxx 128 (4x32) kwords sa2-99 - sa2-102 10111xxxxx 128 (4x32) kwords sa2-103 - sa2-106 11000xxxxx 128 (4x32) kwords sa2-107 - sa2-110 11001xxxxx 128 (4x32) kwords sa2-111 - sa2-114 11010xxxxx 128 (4x32) kwords sa2-115 - sa2-118 11011xxxxx 128 (4x32) kwords sa2-119 - sa2-122 11100xxxxx 128 (4x32) kwords sa2-123 - sa2-126 11101xxxxx 128 (4x32) kwords sa2-127 - sa2-130 11110xxxxx 128 (4x32) kwords sa2-131 - sa2-134 11111xxxxx 128 (4x32) kwords
36 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information sector protection the am29pdl127h/am29pdl129h features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: persistent sector protection a command sector protection method that replaces the old 12 v controlled protection method. password sector protection a highly sophisticated protection method that requires a password before changes to certain sectors or sec- tor groups are permitted. wp# hardware protection a write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269 in pdl 127 or in sa1-133, sa1-134, sa2-0, sa2-1 in pdl 129. the wp# hardware protection feature is always available, regardless of which of the other two methods are cho- sen. selecting a sector protection mode the device defaults to the persistent sector protection mode. however, to prevents a program or virus from later setting the password mode locking bit, which would cause an unexpected shift from the default per- sistent sector protection mode into the password pro- tection mode, it is recommended that either of two one-time programmable non-volatile bits that perma- nently define which sector protection method be set before the device is first programmed . the persis- tent sector protection mode locking bit perma- nently sets the device to the persistent sector protection mode. the password mode locking bit permanently sets the device to the password sector protection mode. it is not possible to switch between the two protection modes once a locking bit has been set. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at the factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is pro- tected or unprotected. see autoselect command se- quence for details. persistent sector protection the persistent sector protection method replaces the 12 v controlled protection method in previous amd flash devices. this new method provides three differ- ent sector protection states: persistently locked ?the sector is protected and cannot be changed. dynamically locked ?the sector is protected and can be changed by a simple command. unlocked ?the sector is unprotected and can be changed by a simple command. to achieve these states, three types of ?bits? are used: persistent protection bit (ppb) a single persistent (non-volatile) protection bit is as- signed to a maximum four sectors (see the sector ad- dress tables for specific sector protection groupings). all 4 kword boot-block sectors have individual sector persistent protection bits ( ppbs) for greater flexibility. each ppb is individually modifiable through the ppb write command . the device erases all ppbs in parallel. if any ppb re- quires erasure, the device must be instructed to pre- program all of the sector ppbs prior to ppb erasure. otherwise, a previously er ased sector ppbs can po- tentially be over-erased. the flash device does not have a built-in means of preventing sector ppbs over-erasure . persistent protection bit lock (ppb lock) the persistent protection bit lock (ppb lock) is a glo- bal volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are change- able. there is only one ppb lock bit per device. the ppb lock is cleared after power-up or hardware reset. there is no command sequence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dybs is ?0?. each dyb is individually modifiable through the dyb write command. when the parts are first shipped, the ppbs are cleared, the dybs are cleared, and ppb lock is de- faulted to power up in the cleared state ? meaning the ppbs are changeable. when the device is first powered on the dybs power up cleared (sectors not protected). the protection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppbs cleared, the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write command sequences, the dybs will be set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and un- protected conditions. this allows software to easily protect sectors against inadvertent changes yet does
november 24, 2003 am70pdl127cdh/am70pdl129cdh 37 advance information not prevent the easy removal of protection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and difficult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. in- dividual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also limited to 100 erase cycles. the ppb lock bit adds an additional level of protec- tion. once all ppbs are programmed to the desired settings, the ppb lock may be set to ?1?. setting the ppb lock disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the ppb are needed; for example, to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock to disable any further changes to the ppbs during system opera- tion. the wp#/acc write protect pin adds a final level of hardware protection to sectors 0, 1, 268, and 269 in pdl 127 or in sa1-133, sa1-134, sa2-0, sa2-1 in pdl 129. when this pin is low it is not possible to change the contents of these sectors. these sectors generally hold system boot code. the wp#/acc pin can prevent any changes to the boot code that could override the choices made while setting up sector pro- tection during system initialization. it is possible to have sectors that have been persis- tently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unpro- tected. if there is a need to protect some of them, a simple dyb write command sequence is all that is necessary. the dyb write command for the dynamic sectors switch the dybs to signify protected and un- protected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be dis- abled by either putting the device through a power-cy- cle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the de- vice operates normally again. the best protection is achieved by executing the ppb lock bit set command early in the boot code, and pro- tect the boot code by holding wp#/acc = v il . table 11. sector protection schemes table 11 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynami- cally locked or unlocked. the dyb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modi- fied the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sec- tor. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing a dyb/ppb/ppb lock verify command to the device. persistent sector protection mode locking bit like the password mode locking bit, a persistent sec- tor protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit pre- vents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode. password protection mode the password sector protection mode method allows an even higher level of security than the persistent sector protection mode. there are two main differ- dyb ppb ppb lock sector state 000 unprotected?ppb and dyb are changeable 001 unprotected?ppb not changeable, dyb is changeable 010 protected?ppb and dyb are changeable 100 110 011 protected?ppb not changeable, dyb is changeable 101 111
38 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information ences between the persistent sector protection and the password sector protection mode: when the device is first powered on, or comes out of a reset cycle, the ppb lock bit set to the locked state , rather than cleared to the unlocked state. the only means to clear the ppb lock bit is by writ- ing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. once the password mode locking bit is set, the pass- word is permanently set with no means to read, pro- gram, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the pass- word. the password may be correlated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password re- gion, the customer may perform password verify oper- ations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: 1. permanently sets the device to operate using the password protection mode. it is not possible to re- verse this function. 2. disables all further commands to the password re- gion. all program, and read operations are ignored. both of these objectives are important, and if not care- fully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persistent sector protection lock- ing bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the pass- word program and verify commands (see ?password verify command?). the password function works in conjunction with the password mode locking bit, which when set, prevents the password verify com- mand from reading the contents of the password on the pins of the device. write protect (wp#) the write protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 in pdl 127 or in sa1-133, sa1-134, sa2-0, sa2-1 in pdl 129 with- out using v id . this function is provided by the wp# pin and overrides the previously discussed high voltage sector protection method. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the two outermost 4 kword sectors on both ends of the flash array independent of whether it was previously pro- tected or unprotected. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether sectors 0, 1, 268, and 269 in pdl 127 or in sa1-133, sa1-134, sa2-0, sa2-1 in pdl 129 were last set to be protected or unprotected. that is, sector protection or unprotection for these sec- tors depends on whether they were last protected or unprotected using the method described in high volt- age sector protection. note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode lock- ing bit after power-up reset. if the password mode lock bit is also set after a hardware reset (reset# asserted) or a power-up reset, the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. suc- cessful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a ?1? when the password mode lock bit is not set.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 39 advance information if the password mode locking bit is not set, including persistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set com- mand. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persis- tent protection mode. high voltage sector protection sector protection and unprotection may also be imple- mented using programming equipment. the proce- dure requires high voltage (v id ) to be placed on the reset# pin. refer to figure 1 for details on this pro- cedure. note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
40 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information figure 1. in-system sector protection/ sector unprotection algorithms sector protect: write 60h to sector address with a7-a0 = 00000010 set up sector address wait 100 s verify sector protect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7-a0 = 01000010 set up first sector address wait 1.2 ms verify sector unprotect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 remove v id from reset# write reset command sector protect complete remove v id from reset# write reset command sector unprotect complete
november 24, 2003 am70pdl127cdh/am70pdl129cdh 41 advance information temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the re- set# pin, all the previously protected sectors are protected again. figure 2 shows the algorithm, and figure 19 shows the timing diagrams, for this feature. while ppb lock is set, the device cannot enter the temporary sector unprotection mode. figure 2. temporar y sector unprotect operation secsi? (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn) the 128-word secsi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. the secsi sector is located at addresses 000000h-00007fh in both persistent pro- tection mode and password protection mode. it uses indicator bits (dq6, dq7) to indicate the fac- tory-locked and customer-locked status of the part. the system accesses the secsi sector through a command sequence (see ?enter secsi? sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to send- ing commands to the normal address space. factory-locked area (64 words) the factory-locked area of the secsi sector (000000h-00003fh) is locked when the part is shipped, whether or not the area was programmed at the factory. the secsi sector factory-locked indicator bit (dq7) is permanently set to a ?1?. amd offers the expressflash service to program the factory-locked area with a random esn, a customer-defined code, or any combination of the two. because only amd can program and protect the factory-locked area, this method ensures the security of the esn once the product is shipped to the field. contact an amd repre- sentative for details on using amd?s expressflash ser- vice. note that the acc function and unlock bypass modes are not available when the secsi sector is en- abled. customer-lockable area (64 words) the customer-lockable area of the secsi sector (000040h-00007fh) is shipped unprotected, which al- lows the customer to program and optionally lock the area as appropriate for the application. the secsi sector customer-locked indicator bit (dq6) is shipped as ?0? and can be permanently locked to ?1? by issuing the secsi protection bit program command. the secsi sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock by- pass functions are not available when programming the secsi sector. the customer-lockable secsi sector area can be pro- tected using one of the following procedures: follow the secsi sector protection algorithm as shown in figure 3. this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is only appli- cable to the secsi sector. once the secsi sector is locked and verified, the sys- tem must write the exit secsi sector region com- mand sequence to return to reading and writing the remainder of the array. notes: 1. all protected sectors unprotected (if wp#/acc = v il , sectors 0, 1, 268, 269 in pdl 127 or in sa1-133, sa1-134, sa2-0, sa2-1 in pdl 129.will remain protected). 2. all previously protected sectors are protected once again. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
42 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information figure 3. pdl127/9h secsi sector protection algorithm the secsi sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. secsi sector protection bits the secsi sector protection bits prevent program- ming of the secsi sector memory area. once set, the secsi sector memory area contents are non-modifi- able. start secsi tm sector entry write aah to address 555h write 55h to address 2aah write 88h to address 555h secsi sector protection entry write aah to address 555h write 55h to address 2aah write 60h to address 555h plscnt = 1 protect secsi sector: write 68h to sector address with a7?a0 = 00011010 time out 256 s read from sector address with a7?a0 = 00011010 data = 01h? yes yes secsi sector protection completed secsi sector exit write 555h/aah write 2aah/55h write sa0+555h/90h write xxxh/00h verify secsi sector: write 48h to sector address with a7?a0 = 00011010 increment plscnt plscnt = 25? device failed secsi sector entry secsi sector protection secsi sector exit no no
november 24, 2003 am70pdl127cdh/am70pdl129cdh 43 advance information hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe#, ce#f1, ce#f2 or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce#f1 =ce#f2 = v ih or we# = v ih . to initiate a write cycle, ce#f1/ce#f2 and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce#f1 = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 12?15. to terminate reading cfi data, the system must write the reset command. the cfi query mode is not accessible when the device is exe- cuting an embedded program or embedded erase al- gorithm. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 12?15. the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alterna- tively, contact an amd representative for copies of these documents.
44 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information table 12. cfi query identification string table 13. system interface string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 45 advance information table 14. device geometry definition addresses data description 27h 0018h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 00fdh 0000h 0000h 0001h erase block region 2 information (refer to the cfi specification or cfi publication 100) 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100)
46 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information table 15. primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii (reflects modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h sector protect/unprotect scheme 01 =29f040 mode, 02 = 29f016 mode, 03 = 29f400, 04 = 29lv800 mode 4ah 00e7h simultaneous operation 00 = not supported, x = number of sectors excluding bank 1 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 00h = uniform device, 02h = bottom boot device, 03h = top boot device, 04h = both top and bottom 50h 0001h program suspend 0 = not supported, 1 = supported 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0027h bank 1 region information x = number of sectors in bank 1 59h 0060h bank 2 region information x = number of sectors in bank 2 5ah 0060h bank 3 region information x = number of sectors in bank 3 5bh 0027h bank 4 region information x = number of sectors in bank 4
november 24, 2003 am70pdl127cdh/am70pdl129cdh 47 advance information command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 16 defines the valid register command sequences. writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. a reset com- mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#f1/ce#f2 (pdl129h only), whichever happens later. all data is latched on the rising edge of we# or ce#f1/ce#f2 (pdl129h only), whichever happens first. refer to the flash ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. the system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same excep- tion. see the erase suspend/erase resume com- mands section for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the mcp device bus operations section for more informa- tion. the read-only operations ? am29pdl127h and read-only operations ? am29pdl127h tables pro- vide the read parameters, and figure 12 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys- tem was writing to the read mode. once erasure be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au- toselect command. the bank then enters the autose- lect mode. the system may read any number of autoselect codes without reinitiating the command se- quence. table 16 shows the address and data requirements. to determine sector protection information, the system must write to the appropriate bank address (ba) and sector address (sa). ta bl e 4 shows the address range and bank number associated with each sector. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend).
48 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information enter secsi? sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing a random, eight wo rd electronic serial num- ber (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the de- vice to normal operation. the secsi sector is not ac- cessible when the device is executing an embedded program or embedded erase algorithm. table 16 shows the address and data requirements for both command sequences. see also ?secsi? (secured sili- con) sector flash memory region? for further informa- tion. note that the acc function and unlock bypass modes are not available when the secsi sector is en- abled. word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 16 shows the address and data requirements for the program command se- quence. when the embedded program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. refer to the write operation status section for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. note that the secsi sector, autoselect, and cfi functions are unavailable when the secsi sector is enabled. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was success- ful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram data to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two un- lock cycles. this is followed by a third write cycle con- taining the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle un- lock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program com- mand, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 16 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device dam- age may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 3 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figures 12 and 13 for timing diagrams.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 49 advance information figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 16 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status sec- tion for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. note that the secsi sector, autoselect, and cfi functions are un- available when the secsi sector is enabled. if that oc- curs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 14 for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command.table 16 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. note that the secsi sec- tor, autoselect, and cfi functions are unavailable when the secsi sector is enabled. the system must rewrite the command sequence and any additional ad- dresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can de- start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 16 for program command sequence.
50 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information termine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 14 section for timing diagrams. figure 5. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the au- toselect mode, the device reverts to the erase sus- pend mode, and is ready for another valid operation. refer to the autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command (address bits are don?t care). the bank address of the erase-sus- pended bank is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. password program command the password program command permits program- ming the password that is used as part of the hard- ware protection scheme. the actual password is 64-bits long. four password program commands are required to program the password. the system must enter the unlock cycle, password program command (38h) and the program address/data for each portion start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 16 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 51 advance information of the password when programming. there are no pro- visions for entering the 2-cycle unlock cycle, the pass- word program command, and all the password data. there is no special addressing order required for pro- gramming the password. also, when the password is undergoing programming, simultaneous operation is disabled. read operations to any memory location will return the programming status. once programming is complete, the user must issue a read/reset com- mand to return the device to normal operation. once the password is written and verified, the password mode locking bit must be set in order to prevent verifi- cation. the password program command is only ca- pable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm? with the cell remain- ing as a ?0?. the password is all ones when shipped from the factory. all 64-bit password combinations are valid as a password. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is programmed and the user attempts to verify the password, the device will al- ways drive all f?s onto the dq data bus. the password verify command is permitted if the secsi sector is enabled. also, the device will not oper- ate in simultaneous operation when the password verify command is executed. only the password is re- turned regardless of the bank address. the lower two address bits (a1-a0) are valid during the password verify. writing the read/reset command returns the device back to normal operation. password protection mode locking bit program command the password protection mode locking bit program command programs the password protection mode locking bit, which prevents further verifies or updates to the password. once programmed, the password protection mode locking bit cannot be erased! if the password protection mode locking bit is verified as program without margin, the password protection mode locking bit program command can be executed to improve the program margin. once the password protection mode locking bit is programmed, the per- sistent sector protection locking bit program circuitry is disabled, thereby forcing the device to remain in the password protection mode. exiting the mode locking bit program command is accomplished by writing the read/reset command. persistent sector protection mode locking bit program command the persistent sector protection mode locking bit program command programs the persistent sector protection mode locking bit, which prevents the pass- word mode locking bit from ever being programmed. if the persistent sector protection mode locking bit is verified as programmed without margin, the persistent sector protection mode locking bit program com- mand should be reissued to improve program margin. by disabling the program circuitry of the password mode locking bit, the device is forced to remain in the persistent sector protection mode of operation, once this bit is set. exiting the persistent protection mode locking bit program command is accomplished by writing the read/reset command. secsi sector protection bit program command the secsi sector protection bit program command programs the secsi sector protection bit, which pre- vents the secsi sector memory from being cleared. if the secsi sector protection bit is verified as pro- grammed without margin, the secsi sector protection bit program command should be reissued to improve program margin. exiting the v cc -level secsi sector protection bit program command is accomplished by writing the read/reset command. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully exe- cuted. there is no ppb lock bit clear command. once the ppb lock bit is set, it cannot be cleared un- less the device is taken through a power-on clear or the password unlock command is executed. upon set- ting the ppb lock bit, the ppbs are latched into the dybs. if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on reset cycle. exiting the ppb lock bit set command is accomplished by writing the read/reset command (only in the persistent protection mode). dyb write command the dyb write command is used to set or clear a dyb for a given sector. the high order address bits a22-a12 for pdl127 and (a21?a12) for pdl129h are issued at the same time as the code 01h or 00h on dq7-dq0. all other dq data bus pins are ignored dur- ing the data write cycle. the dybs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. the dybs are cleared at power-up or hard- ware reset. exiting the dyb write command is accom- plished by writing the read/reset command.
52 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become ac- cessible for modification. the exact password must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 2 s at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. if the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. once the password unlock command is entered, the ry/by# indicates that the device is busy. approxi- mately 1 s is required for each portion of the unlock. once the first portion of the password unlock com- pletes (ry/by# is not low or dq6 does not toggle when read), the next part of the password is written. the system must thus monitor ry/by# or the status bits to confirm when to write the next portion of the password. seven cycles are required to successfully clear the ppb lock bit. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually pro- grammed (but is bulk erased with the other ppbs). the specific sector address (a21?a12) are written at the same time as the program command 60h with a6 = 0. if the ppb lock bit is set and the corresponding ppb is set for the sector, the ppb program command will not execute and the command will time-out without programming the ppb. after programming a ppb, two additional cycles are needed to determine whether the ppb has been pro- grammed with margin. if the ppb has been pro- grammed without margin, the program command should be reissued to improve the program margin. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs be- yond 100 cycles is not guaranteed. the ppb program command does not follow the em- bedded program algorithm. all ppb erase command the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually eras- ing a specific ppb. unlike the ppb program, no spe- cific sector address is required. however, when the ppb erase command is written all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command will not execute and the com- mand will time-out without erasing the ppbs. after erasing the ppbs, two additional cycles are needed to determine whether the ppb has been erased with margin. if the ppbs has been erased without margin, the erase command should be reissued to improve the program margin. it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase command. if the user attempts to erase a cleared ppb, over-era- sure may occur making it difficult to program the ppb at a later time. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. dyb write command the dyb write command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sector is pro- tected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, remov- ing power or resetting the device will clear the dybs. the bank address is latched when the command is written. ppb lock bit set command the ppb lock bit set command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sec- tor is protected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device will clear the dybs. the bank address is latched when the com- mand is written. ppb status command the programming of the ppb for a given sector can be verified by writing a ppb status verify command to the device. ppb lock bit status command the programming of the ppb lock bit for a given sec- tor can be verified by writing a ppb lock bit status ver- ify command to the device. sector protection status command the programming of either the ppb or dyb for a given sector or sector group can be verified by writing a sec- tor protection status command to the device. note that there is no single command to independently verify the programming of a dyb for a given sector group.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 53 advance information command definitions tables legend: ba = address of bank switching to autoselect mode, bypass mode, or erase operation. determined by a22:a20, (a21:a20 for pdl129) see ta b l e s 4 and 5 for more detail. pa = program address (a22:a0) (a21:a0 for pdl129). addresses latch on falling edge of we# or ce#f1/ce#f2 (pdl129 only) pulse, whichever happens later. pd = program data (dq15:dq0) written to location pa. data latches on rising edge of we# or ce#f1/ce#f2 (pdl129 only) pulse, whichever happens first. ra = read address (a22:a0) (a21:a0 for pdl129). rd = read data (dq15:dq0) from location ra. sa = sector address (a22:a12) (a21:a12 for pdl129) for verifying (in autoselect mode) or erasing. wd = write data. see ?configuration register? definition for specific write data. data latched on rising edge of we#. x = don?t care notes: 1. see ta bl e 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to reading array (or to erase-suspend-read mode if previously in erase suspend) when bank is in autoselect mode, or if dq5 goes high (while bank is providing status information). 7. fourth cycle of autoselect command sequence is a read cycle. system must provide bank address to obtain manufacturer id or device id information. see autoselect command sequence section for more information. 8. the data is c0h for factory or customer locked and 80h for factory locked. 9. the data is 00h for an unprotected sector group and 01h for a protected sector group. 10. device id must be read across cycles 4, 5, and 6. 20 for am29pdl127h and 21 for am29pdl129h. 11. system may read and program in non-erasing sectors, or enter autoselect mode, when in program/erase suspend mode. program/erase suspend command is valid only during a sector erase operation, and requires bank address. 12. program/erase resume command is valid only during erase suspend mode, and requires bank address. 13. command is valid when device is ready to read array data or when device is in autoselect mode. 14. wp#/acc must be at v id during the entire operation of command. 15. unlock bypass entry command is required prior to any unlock bypass operation. unlock bypass reset command is required to return to the reading array. table 16. memory array command definitions command (notes) cycles bus cycles (notes 1?4) addr data addr data addr data addr data addr data addr data read (5) 1 ra rd reset (6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 (ba)x00 01 device id (10) 6 555 aa 2aa 55 555 90 (ba)x01 7e (ba)x0e (note 10) (ba)x0f 00 secsi sector factory protect (8) 4 555 aa 2aa 55 555 90 x03 (see note 8) sector group protect verify (9) 4 555 aaa 2aa 55 555 90 (sa)x02 xx00/ xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (11) 1 ba b0 program/erase resume (12) 1 ba 30 cfi query (13) 1 55 98 accelerated program (15) 2 xx a0 pa pd unlock bypass entry (15) 3 555 aa 2aa 55 555 20 unlock bypass program (15) 2 xx a0 pa pd unlock bypass erase (15) 2 xx 80 xx 10 unlock bypass cfi (13, 15) 1 xx 98 unlock bypass reset (15) 2 xxx 90 xxx 00
54 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information legend: dyb = dynamic protection bit ow = address (a7:a0) is (00011010) pd[3:0] = password data (1 of 4 portions) ppb = persistent protection bit pwa = password address. a1:a0 selects portion of password. pwd = password data being verified. pl = password protection mode lock address (a7:a0) is (00001010) rd(0) = read data dq0 for protection indicator bit. rd(1) = read data dq1 for ppb lock status. sa = sector address where security command applies. address bits a21:a12 uniquely select any sector. sl = persistent protection mode lock address (a7:a0) is (00010010) wp = ppb address (a7:a0) is (00000010) (note16) x = don?t care ppmlb = password protection mode locking bit spmlb = persistent protection mode locking bit 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. the reset command returns device to reading array. 6. cycle 4 programs the addressed locking bit. cycles 5 and 6 validate bit has been fully programmed when dq0 = 1. if dq0 = 0 in cycle 6, program command must be issued and verified again. 7. data is latched on the rising edge of we#. 8. entire command sequence must be entered for each portion of password. 9. command sequence returns ffh if ppmlb is set. 10. the password is written over four consecutive cycles, at addresses 0-3. 11. a 2 s timeout is required between any two portions of password. 12. a 100 s timeout is required between cycles 4 and 5. 13. a 1.2 ms timeout is required between cycles 4 and 5. 14. cycle 4 erases all ppbs. cycles 5 and 6 validate bits have been fully erased when dq0 = 0. if dq0 = 1 in cycle 6, erase command must be issued and verified again. before issuing erase command, all ppbs should be programmed to prevent ppb overerasure. 15. dq1 = 1 if ppb locked, 0 if unlocked. 16. for pdl128g and pdl640g, the wp address is 0111010. the ep address (ppb erase address) is 1111010. 17. following the final cycle of the command sequence, the user must write the first three cycles of the autoselect command and then write a reset command. 18. if checking the dyb status of sectors in multiple banks, the user must follow note 17 before crossing a bank boundary. table 17. sector protection command definitions command (notes) cycles bus cycles (notes 1-4) addr data addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secsi sector entry 3 555 aa 2aa 55 555 88 secsi sector exit 4 555 aa 2aa 55 555 90 xx 00 secsi protection bit program (5, 6) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd(0) secsi protection bit status 5 555 aa 2aa 55 555 60 ow 48 ow rd(0) password program (5, 7, 8) 4 555 aa 2aa 55 555 38 xx[0-3] pd[0-3] password verify (6, 8, 9) 4 555 aa 2aa 55 555 c8 pwa[0-3] pwd[0-3] password unlock (7, 10, 11) 7 555 aa 2aa 55 555 28 pwa[0] pwd[0] pwa[1] pwd[1] pwa[2] pwd[2] pwa[3] pwd[3] ppb program (5, 6, 12, 17) 6 555 aa 2aa 55 555 60 (sa)wp 68 (sa)wp 48 (sa)wp rd(0) ppb status 5 555 aa 2aa 55 555 60 (sa)wp 48 (sa)wp rd (0) all ppb erase (5, 6, 13, 14) 6 555 aa 2aa 55 555 60 wp 60 (sa) 40 (sa)wp rd(0) ppb lock bit set (17) 3 555 aa 2aa 55 555 78 ppb lock bit status (15) 4 555 aa 2aa 55 555 58 sa rd(1) dyb write (7) 4 555 aa 2aa 55 555 48 sa x1 dyb erase (7) 4 555 aa 2aa 55 555 48 sa x0 dyb status (6, 18) 4 555 aa 2aa 55 555 58 sa rd(0) ppmlb program (5, 6, 12) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status (5) 5 555 aa 2aa 55 555 60 pl 48 pl rd(0) spmlb program (5, 6, 12) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status (5) 5 555 aa 2aa 55 555 60 sl 48 sl rd(0)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 55 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 18 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is com- plete or in progress. the device also provides a hard- ware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase sus- pend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 400 s, then the bank returns to the read mode. if not all selected sec- tors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq15?dq0 on the following read cycles. just prior to the completion of an embedded program or erase op- eration, dq7 may change asynchronously with dq15?dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 may be still invalid. valid data on dq15?dq0 will appear on suc- cessive read cycles. table 18 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. figure 5 in the flash ac characteristics section shows the data# polling timing diagram. figure 6. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
56 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-sus- pend-read mode. table 18 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce#f1 to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 400 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are pro- tected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase sus- pend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# poll- ing). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 18 shows the outputs for toggle bit i on dq6. figure 6 shows the toggle bit algorithm. figure 17 in the ?flash ac characteristics? section shows the tog- gle bit timing diagrams. figure 18 shows the differ- ences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. figure 7. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 57 advance information dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce#f1 to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 18 to compare out- puts for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsection. figure 17 shows the toggle bit timing diagram. figure 18 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 6). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 18 shows the status of dq3 relative to the other status bits.
58 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information table 18. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
november 24, 2003 am70pdl127cdh/am70pdl129cdh 59 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?55 c to +125 c ambient temperature with power applied. . . . . . . . . . . . . . . ?40 c to +85 c voltage with respect to ground v cc f, v cc s (note 1) . . . . . . . . . . . . ?0.5 v to +4.0 v reset# (note 2) . . . . . . . . . . . .?0.5 v to +12.5 v wp#/acc . . . . . . . . . . . . . . . . . . ?0.5 v to +10.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 8. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 9. 2. minimum dc input voltage on pins reset#, and wp#/acc is ?0.5 v. during voltage transitions, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8. maximum dc input voltage on pin reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c v cc f/v cc s supply voltages v cc f/v cc s for standard voltage range . . 2.7 v to 3.1 v operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
60 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information dc characteristics cmos compatible notes: 1. valid ce#f1/ce#f2 conditions (pdl129 only): (ce#f1= v il , ce#f2= v ih ) or (ce#f1= v ih , ce#f2= v il ) 2. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v ccmax . 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 150 ns. typical sleep mode current is 1 a. 6. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe#, reset# input load current v cc = v cc max ; v id = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; v id = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , oe# = v ih v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2, 3) oe# = v ih , v cc = v cc max (note 1) 5 mhz 20 30 ma 10 mhz 45 55 i cc2 v cc active write current (notes 1, 3, 4) oe# = v ih , we# = v il 15 25 ma i cc3 v cc standby current (note 3) ce#f1, ce#f2 (pdl129 only), reset#, wp/acc# = v io 0.3 v 15a i cc4 v cc reset current (note 3) reset# = v ss 0.3 v, ce# = v ss 15a i cc5 automatic sleep mode (notes 3, 5) v ih = v io 0.3 v; v il = v ss 0.3 v, ce# = v ss 15a i cc6 v cc active read-while-program current (notes 1, 2, 3) oe# = v ih word 21 45 ma i cc7 v cc active read-while-erase current (notes 1, 2, 3) oe# = v ih word 21 45 ma i cc8 v cc active program-while-erase- suspended current (notes 1, 3, 6) oe# = v ih 17 25 ma v il input low voltage v io = 2.7?3.6 v ?0.5 0.8 v v ih input high voltage v io = 2.7?3.6 v 2.0 v cc +0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 2.0 ma, v cc = v cc min 0.4 v v oh output high voltage i oh = ?2.0 ma, v cc = v cc min 2.4 v v lko low v cc lock-out voltage (note 6) 2.3 2.5 v
november 24, 2003 am70pdl127cdh/am70pdl129cdh 61 advance information psram dc characteristics recommended dc operating conditions (note 1) notes: 1. t a = -40 to 85 c, otherwise specified. 2. overshoot: v cc + 1.0 v in case of pulse width 20 ns. 3. undershoot: -1.0 v in case of pulse width 20 ns. 4. overshoot and undershoot are sampled, not 100% tested. capacitance (f= 1mhz, ta = 25 c) note: capacitance is sampled, not 100% tested. dc and operating characteristics note: typical values are tested at v cc = 2.9 v, t a = 25 c and not guaranteed. item symbol min typ max unit supply voltage v cc 2.7 2.9 3.1 v ground v ss 000v input high voltage v ih 2.2 - v cc + 0.3 (note 2) v input low voltage v il -0.3 (note 3) - 0.6 v item symbol test condition min max unit input capacitance c in v in = 0 v - 8 pf input/output capacitance c io v io = 0 v - 10 pf item symbol test conditions min typ max unit input leakage current i li v in = v ss to v cc -1 - 1 s output leakage current i lo cs#1s= v ih , cs2s= v ih or we#= v il , v io = v ss to v cc -1 - 1 s average operating current i cc1 cycle time = 1ms, 100% duty, i io = 0 ma, cs#1s 0.2 v, cs2s v cc 0.2 v or v in v cc -0.2 v -307ma i cc2 cycle time = min, i io = 0 ma, 100% duty, i io = 0 ma, cs#1s = v il , cs2s = v ih , v in =v il or v ih --35ma output low voltage v ol i ol = 2.1 ma - - 0.4 v output high voltage v oh i oh = -1.0 ma 2.4 - - v standby current (cmos) i sb1 cs#1s v cc -0.2 v, cs2s v cc -0.2 v, other inputs= v ss to v cc --80 s deep power down i sbd cs2s 0.2v, other inputs= v ss to v cc --20 s
62 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information test conditions table 19. test specifications key to switching waveforms 2.7 k ? c l 6.2 k ? 3.1 v device under te s t note: diodes are in3064 or equivalent figure 10. test setup, v io = 2.7 ? 3.1 v test condition 66, 85 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 11. input waveforms and measurement levels
november 24, 2003 am70pdl127cdh/am70pdl129cdh 63 advance information flash ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset#1 ry/by#1 ry/by#1 t rp t ready reset timings not during embedded algorithms t ready ce#f1, ce#f2 (pdl129 only), oe# t rh ce#f1, ce#f2 (pdl129 only), oe# reset timings during embedded algorithms reset#1 t rp t rb figure 12. reset timings
64 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information flash ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?flash erase and programming performance? section for more information. parameter speed jedec std description 66 85 unit t avav t wc write cycle time (note 1) min 65 85 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 35 ns t aht address hold time from ce#1f or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time (ce#f1 to we#) min 0 ns t elwl t cs ce#f1 setup time min 0 ns t ehwh t wh we# hold time (ce#f1 to we#) min 0 ns t wheh t ch ce#f1 hold time min 0 ns t wlwh t wp write pulse width min 40 ns t whdl t wph write pulse width high min 25 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) word typ 6 s t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
november 24, 2003 am70pdl127cdh/am70pdl129cdh 65 advance information flash ac characteristics oe# we# ce#1f or ce#2f (pdl129 only) v cc f data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. 3 . for pdl129 during ce# transitions the other ce# pin = v ih. figure 13. program operation timings wp#/acc t vhh v hh v il or v ih v il or v ih t vhh figure 14. accelerated program timing diagram
66 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information flash ac characteristics oe# ce#1f (pdl129 only) addresses v cc f we# data 2aah sadd t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sadd = sector address (for sector erase), va = valid address for reading status data (see ?flash write operation status?. 2 . for pdl129 during ce# transitions the other ce# pin = v ih . figure 15. chip/sector erase operation timings
november 24, 2003 am70pdl127cdh/am70pdl129cdh 67 advance information flash ac characteristics oe# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce#f controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w ce#1f or ce#2f (pdl129 only) figure 16. back-to-back read/write cycle timings we# ce#1f or ce#2f (pdl129 only) oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 17. data# polling timings (during embedded algorithms)
68 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information flash ac characteristics oe# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# ce#1f or ce#2f (pdl129 only) note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 18. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce#f1 to toggle dq2 and dq6. figure 19. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
november 24, 2003 am70pdl127cdh/am70pdl129cdh 69 advance information flash ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce#1f or ce#2f (pdl129 only) we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 20. temporary sector unprotect timing diagram
70 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information flash ac characteristics sector/sector block protect: 150 s, sector/sector block unprot ect: 15 ms 1 s reset# sadd, a6, a1, a0 data ce#1f or ce#2f (pdl129 only) we# oe# 60h 60h 40h valid* valid* valid* status sector/sector block protect or unprotect verify v id v ih 1. for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0, sadd = sector address. 2. for pdl129 during ce#f1 transitions the other ce#f1 pin = v ih . figure 21. sector/sector block protect and unprotect timing diagram
november 24, 2003 am70pdl127cdh/am70pdl129cdh 71 advance information flash ac characteristics alternate ce#f1 controlled erase and program operations notes: 1. not 100% tested. 2. see the ?flash erase and programming performance? section for more information. parameter speed jedec std description 66 85 unit t avav t wc write cycle time (note 1) min 66 85 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 35 ns t dveh t ds data setup time min 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce#f1 pulse width min 40 ns t ehel t cph ce#f1 pulse width high min 25 ns t whwh1 t whwh1 programming operation (note 2) word typ 6 s t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec
72 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information flash ac characteristics t ghel t ws oe# ce#f1 or ce#f2 (pdl129 only) we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sadd for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sadd = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. figure 22. flash alternate ce#f1 controlled write (erase/progra m) operation timings
november 24, 2003 am70pdl127cdh/am70pdl129cdh 73 advance information psram ac characteristics ce#s timing figure 23. timing diagram for alternating between pseudo sram to flash note: after v cc reaches v cc (min), wait 200 s with cs#1s and cs2s high. the device will enter into normal operation. figure 24. timing waveform of power-up parameter description test setup all speeds unit jedec std ?t ccr ce#s recover time ? min 0 ns ce#1ps t ccr t ccr ce2ps v cc v cc (min) min. 0 ns cs2s cs#1s power up mode normal operation min. 200 s
74 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information psram ac characteristics functional description note: ?x? means don?t care. (must be low or high state). absolute maximum ratings note: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 second may affect reliability. cs#1s cs2s oe# we# lb# ub# i/o 1-8 i/o 9-16 mode power h h x x x x high-z high-z deselected standby x l x x x x high-z high-z deselected deep power down l h x x h h high-z high-z deselected standby l h h h l x high-z high-z output disabled active l h h h x l high-z high-z output disabled active lhlhlhd out high-z lower byte read active lhlhhlhigh-zd out upper byte read active lhlhlld out d out word read active lhxllhd in high-z lower byte write active l hxllld in d in word write active item symbol ratings unit voltage on any pin relative to v ss v in , v out -0.2 to v cc + 0.3v v voltage on v cc supply relative to v ss v cc -0.2 to 3.6 v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c
november 24, 2003 am70pdl127cdh/am70pdl129cdh 75 advance information psram ac characteristics figure 25. standby mode state machines standby mode characteristic ac characteristics (v cc = 2.7-3.1 v, ta= -40 to 85 c) t wp (min)= 70 ns for continuous write operation over 50 times. cs2s =v il cs#1s =v ih cs #1=v il , ub or/and lb=v il power on initial state (wait 200 s) active standby mode deep power down mode cs2s =v ih cs#1s=v ih and cs2s =v ih cs2s =v il cs#1s =v ih , cs2s =v ih cs2s =v ih power mode memory cell data standby current ( a) wait time ( s) standby valid 80 0 deep power down invalid 20 200 parameter list symbol speed bins units 66/85 ns min max read read cycle time t rc 70 - ns address access time t aa -70ns chip select to output t co -70ns output enable to valid output t oe -35ns ub#, lb# access time t ba -70ns chip select to low-z output t lz 10 - ns ub#, lb# enable to low-z output t blz 10 - ns output enable to low-z output t olz 5-ns chip disable to high-z output t hz 025ns ub#, lb# disable to high-z output t bhz 025ns output disable to high-z output t ohz 025ns output hold from address change t oh 5-ns write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns address set-up time t as 0-ns address valid to end of write t aw 60 - ns ub#, lb# valid to end of write t bw 60 - ns write pulse width t wp 55 (note 1) -ns write recovery time t wr 0-ns write to output high-z t whz 025ns data to write time overlap t dw 30 - ns data hold from write time t dh 0-ns end write to output low-z t ow 5-ns
76 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information timing diagrams figure 26. timing waveform of read cycle 1 figure 27. timing waveform of read cycle 2 notes: 1. t hz and t oz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max) is less than t lz (min) both for a given device and from device interconnection. 3. t oe (max) is met only when oe# becomes enabled after t aa (max). 4. if invalid address signals shorter than min. t rc are continuously repeated for over 4 us, the device needs a normal read timing (t rc ) or needs to sustain standby state for min. t rc at least once in every 4 us. address data out previous data valid data valid t aa t rc t oh data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t co address cs#1s ub #, lb# oe# data out
november 24, 2003 am70pdl127cdh/am70pdl129cdh 77 advance information timing diagrams figure 28. timing waveform of write cycle 1 figure 29. timing waveform of write cycle 2 address data undefined ub#, lb# we# data in data out t wc t cw(2) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs#1s t wr(4) address data valid ub#, lb# we# data in data out high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs#1s
78 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information timing diagrams notes: write cycle 1. a write occurs during the overlap (t wp ) of low cs#1s and low we#. a write begins when cs#1s goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs#1s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs#1s going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs#1s or we# going high. notes: deep power down mode 1. when you toggle cs2s pin low, the device gets into the deep power down mode after 0.5 ms suspend period. 2. to return to normal operation, the device needs wake-up period. 3. wake up sequence is just the same as power up sequence. figure 30. timing waveform of write cycle 3 address data valid ub#, lb# we# data in data out high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs#1s cs2s mode deep power down mode normal operation 0.5 s 200 s normal operation suspend wake up cs#1s
november 24, 2003 am70pdl127cdh/am70pdl129cdh 79 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. all values are subject to change. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. all values are subject to change. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see tables table 16 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. package pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. flash data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.4 5 sec excludes 00h programming prior to erasure (note 4) chip erase time 108 sec word program time 6 210 s excludes system level overhead (note 5) accelerated word program time 4 120 s chip program time (note 3) 50 200 sec description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 11 14 pf c out output capacitance v out = 0 12 16 pf c in2 control pin capacitance v in = 0 14 16 pf c in3 wp#/acc pin capacitance v in = 0 17 20 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
80 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information general description (lv640m) the am29lv640mh is a 64 mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words. the device has an 8-bit/16-bit bus and can be programmed either in the host system or in standard eprom programmers. an access time of 110 ns is available. each device re- quires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program (acc) feature pro- vides shorter programming times through increased current on the wp#/acc input. this feature is in- tended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase oper- ation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to deter- mine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program sus- pend/program resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the write protect (wp#) feature protects the first or last sector by asserting a logic low on the wp#/acc pin. the protected sector will still be protected even during accelerated programming. the secsi ? (secured silicon) sector provides a 128-word area for code or data that can be perma- nently protected. once this sector is protected, no fur- ther changes within the sector can occur. amd mirrorbit flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 81 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a21:a0 in word mode. 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector group protection and unprotection? section. 3. if wp# = v il , the first or last sector remains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?sector group protection and unprotection?. all sectors are unprotected when shipped from the factory (the secsi sector may be factory protected depending on version ordered.) 4. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only operations table for timing speci- fications and to figure 14 for the timing diagram. refer to the dc characteristics table for the active current specification on reading array data. operation ce# oe# we# reset# wp# acc addresses (note 2) dq0? dq7 dq8?dq 15 read l l h h xx a in d out d out write (program/erase) l h l h (note 3) x a in (note 4) (note 4) accelerated program l h l h (note 3) v hh a in (note 4) (note 4) standby v cc 0.3 v xx v cc 0.3 v xh x high-z high-z output disable l h h h xx x high-z high-z reset x x x l xx x high-z high-z sector group protect (note 2) lhl v id hx sa, a6 =l, a3=l, a2=l, a1=h, a0=l (note 4) x sector group unprotect (note 2) lhl v id hx sa, a6=h, a3=l, a2=l, a1=h, a0=l (note 4) x temporary sector group unprotect xxx v id hx a in (note 4) (note 4)
82 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words/8 bytes. the appropriate page is selected by the higher address bits a(max)?a2. ad- dress bits a1?a0 in word mode (a1?a-1 in byte mode) determine the specific word within a page. this is an asynchronous operation; the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pa c c . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode ac- cesses are obtained by keeping the ?read-page ad- dresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?word/byte program command sequence? section has details on programming data to the device using both standard and unlock bypass command se- quences. an erase operation can erase one sector, multiple sec- tors, or the entire device. ta bl e 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac char- acteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated program- ming, or device damage may result. in addition, no ex- ternal pullup is necessary since the wp#/acc pin has internal pullup to v cc. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more informa- tion. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device re- quires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. refer to the dc characteristics table for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and always available to the system.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 83 advance information refer to the dc characteristics table for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# pa- rameters and to figure 16 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
84 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information table 2. sector address table sector a21?a15 sector size (kwords) 16-bit address range (in hexadecimal) sa0 0000000 32 000000?007fff sa1 0000001 32 008000?00ffff sa2 0000010 32 010000?017fff sa3 0000011 32 018000?01ffff sa4 0000100 32 020000?027fff sa5 0000101 32 028000?02ffff sa6 0000110 32 030000?037fff sa7 0000111 32 038000?03ffff sa8 0001000 32 040000?047fff sa9 0001001 32 048000?04ffff sa10 0001010 32 050000?057fff sa11 0001011 32 058000?05ffff sa12 0001100 32 060000?067fff sa13 0001101 32 068000?06ffff sa14 0001110 32 070000?077fff sa15 0001111 32 078000?07ffff sa16 0010000 32 080000?087fff sa17 0010001 32 088000?08ffff sa18 0010010 32 090000?097fff sa19 0010011 32 098000?09ffff sa20 0010100 32 0a000 0?0a7fff sa21 0010101 32 0a80 00?0affff sa22 0010110 32 0b000 0?0b7fff sa23 0010111 32 0b80 00?0bffff sa24 0011000 32 0c00 00?0c7fff sa25 0011001 32 0c8 000?0cffff sa26 0011010 32 0d00 00?0d7fff sa27 0011011 32 0d8 000?0dffff sa28 0011100 32 0e000 0?0e7fff sa29 0011101 32 0e80 00?0effff sa30 0011110 32 0f00 00?0f7fff sa31 0011111 32 0f8 000?0fffff sa32 0100000 32 100000?107fff sa33 0100001 32 108000?10ffff sa34 0100010 32 110000?117fff sa35 0100011 32 118000?11ffff sa36 0100100 32 120000?127fff sa37 0100101 32 128000?12ffff sa38 0100110 32 130000?137fff sa39 0100111 32 138000?13ffff sa40 0101000 32 140000?147fff sa41 0101001 32 148000?14ffff sa42 0101010 32 150000?157fff sa43 0101011 32 158000?15ffff
november 24, 2003 am70pdl127cdh/am70pdl129cdh 85 advance information sa44 0101100 32 160000?167fff sa45 0101101 32 168000?16ffff sa46 0101110 32 170000?177fff sa47 0101111 32 178000?17ffff sa48 0110000 32 180000?187fff sa49 0110001 32 188000?18ffff sa50 0110010 32 190000?197fff sa51 0110011 32 198000?19ffff sa52 0110100 32 1a000 0?1a7fff sa53 0110101 32 1a80 00?1affff sa54 0110110 32 1b000 0?1b7fff sa55 0110111 32 1b80 00?1bffff sa56 0111000 32 1c00 00?1c7fff sa57 0111001 32 1c8 000?1cffff sa58 0111010 32 1d00 00?1d7fff sa59 0111011 32 1d8 000?1dffff sa60 0111100 32 1e000 0?1e7fff sa61 0111101 32 1e80 00?1effff sa62 0111110 32 1f00 00?1f7fff sa63 0111111 32 1f8 000?1fffff sa64 1000000 32 200000?207fff sa65 1000001 32 208000?20ffff sa66 1000010 32 210000?217fff sa67 1000011 32 218000?21ffff sa68 1000100 32 220000?227fff sa69 1000101 32 228000?22ffff sa70 1000110 32 230000?237fff sa71 1000111 32 238000?23ffff sa72 1001000 32 240000?247fff sa73 1001001 32 248000?24ffff sa74 1001010 32 250000?257fff sa75 1001011 32 258000?25ffff sa76 1001100 32 260000?267fff sa77 1001101 32 268000?26ffff sa78 1001110 32 270000?277fff sa79 1001111 32 278000?27ffff sa80 1010000 32 280000?287fff sa81 1010001 32 288000?28ffff sa82 1010010 32 290000?297fff sa83 1010011 32 298000?29ffff sa84 1010100 32 2a000 0?2a7fff sa85 1010101 32 2a80 00?2affff sa86 1010110 32 2b000 0?2b7fff sa87 1010111 32 2b80 00?2bffff sa88 1011000 32 2c00 00?2c7fff table 2. sector address table (continued) sector a21?a15 sector size (kwords) 16-bit address range (in hexadecimal)
86 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information sa89 1011001 32 2c8 000?2cffff sa90 1011010 32 2d00 00?2d7fff sa91 1011011 32 2d8 000?2dffff sa92 1011100 32 2e000 0?2e7fff sa93 1011101 32 2e80 00?2effff sa94 1011110 32 2f00 00?2f7fff sa95 1011111 32 2f8 000?2fffff sa96 1100000 32 300000?307fff sa97 1100001 32 308000?30ffff sa98 1100010 32 310000?317fff sa99 1100011 32 318000?31ffff sa100 1100100 32 320000?327fff sa101 1100101 32 328000?32ffff sa102 1100110 32 330000?337fff sa103 1100111 32 338000?33ffff sa104 1101000 32 340000?347fff sa105 1101001 32 348000?34ffff sa106 1101010 32 350000?357fff sa107 1101011 32 358000?35ffff sa108 1101100 32 360000?367fff sa109 1101101 32 368000?36ffff sa110 1101110 32 370000?377fff sa111 1101111 32 378000?37ffff sa112 1110000 32 380000?387fff sa113 1110001 32 388000?38ffff sa114 1110010 32 390000?397fff sa115 1110011 32 398000?39ffff sa116 1110100 32 3a000 0?3a7fff sa117 1110101 32 3a80 00?3affff sa118 1110110 32 3b000 0?3b7fff sa119 1110111 32 3b80 00?3bffff sa120 1111000 32 3c00 00?3c7fff sa121 1111001 32 3c8 000?3cffff sa122 1111010 32 3d00 00?3d7fff sa123 1111011 32 3d8 000?3dffff sa124 1111100 32 3e000 0?3e7fff sa125 1111101 32 3e80 00?3effff sa126 1111110 32 3f00 00?3f7fff sa127 1111111 32 3f8 000?3fffff table 2. sector address table (continued) sector a21?a15 sector size (kwords) 16-bit address range (in hexadecimal)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 87 advance information sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see ta b l e 4 ). the hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. sector group protection/unprotection can be implemented via two methods. sector protection/unprotection requires v id on the re- set# pin only, and can be implemented either in-sys- tem or via programming equipment. figure 2 shows the algorithms and figure 24 shows the timing dia- gram. this method uses standard microprocessor bus cycle timing. for sector group unprotect, all unpro- tected sector groups must first be protected prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and pro- tecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. con- tact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the autoselect mode section for details. table 3. sector group protection/unprotection address table sector group a21?a15 sa0 0000000 sa1 0000001 sa2 0000010 sa3 0000011 sa4?sa7 00001xx sa8?sa11 00010xx sa12?sa15 00011xx sa16?sa19 00100xx sa20?sa23 00101xx sa24?sa27 00110xx sa28?sa31 00111xx sa32?sa35 01000xx sa36?sa39 01001xx sa40?sa43 01010xx sa44?sa47 01011xx sa48?sa51 01100xx sa52?sa55 01101xx sa56?sa59 01110xx sa60?sa63 01111xx sa64?sa67 10000xx sa68?sa71 10001xx sa72?sa75 10010xx sa76?sa79 10011xx sa80?sa83 10100xx sa84?sa87 10101xx sa88?sa91 10110xx sa92?sa95 10111xx sa96?sa99 11000xx sa100?sa103 11001xx sa104?sa107 11010xx sa108?sa111 11011xx sa112?sa115 11100xx sa116?sa119 11101xx sa120?sa123 11110xx sa124 1111100 sa125 1111101 sa126 1111110 sa127 1111111 sector group a21?a15
88 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector without using v id . write protect is one of two functions pro- vided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method de- scribed in ?sector group protection and unprotection?. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is increased. see the table in ?dc characteristics?. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether the first or last sector was pre- viously set to be protected or unprotected using the method described in ?sector group protection and unprotection?. note: no external pullup is necessary since the wp#/acc pin has internal pullup to v cc . temporary sector group unprotect ( note: in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see ta b l e 4 ). this feature allows temporary unprotection of previ- ously protected sector groups to change data in-sys- tem. the sector group unprotect mode is activated by setting the reset# pin to v id . during this mode, for- merly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previously protected sector groups are protected again. figure 1 shows the algorithm, and figure 23 shows the timing diagrams, for this feature. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 89 advance information figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6?a0 = 0xx0010 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address with a6?a0 = 0xx0010 read from sector group address with a6?a0 = 0xx0010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6?a0 = 1xx0010 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6?a0 = 1xx0010 read from sector group address with a6?a0 = 1xx0010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
90 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 128 words in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the secu- rity of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secsi sec- tor unprotected, allowing customers to program the sector after receiving the device. the customer-lock- able version also has the secsi sector indicator bit permanently set to a ?0.? thus, the secsi sector indi- cator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the secsi sector address space in this device is allo- cated as follows: the system accesses the secsi sector through a command sequence (see ?enter secsi sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the first sector (sa0). this mode of operation continues until the system is- sues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. customer lockable: secsi sector not programmed or protected at the factory as an alternative to the factory-locked version, the de- vice may be ordered such that the customer may pro- gram and protect the 128-word secsi sector. see ta bl e 5 for secsi sector addressing. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass meth- ods, in addition to the standard programming com- mand sequence. see command definitions . programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 3. once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequence to return to reading and writing within the remainder of the array. figure 3. secsi sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to tables 10 and 11 table 4. secsi sector contents secsi sector address range standard factory locked expressflash factory locked customer lockable x16 000000h? 000007h esn esn or determined by customer determined by customer 000008h? 00007fh unavailable determined by customer write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
november 24, 2003 am70pdl127cdh/am70pdl129cdh 91 advance information for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6 ? 9 . to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6 ? 9 . the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alterna- tively, contact an amd representative for copies of these documents.
92 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information table 5. cfi query identification string addresses (x16) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 93 advance information table 6. system interface string table 7. device geometry definition addresses (x16) data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0007h typical timeout per single byte/word write 2 n s 20h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0001h max. timeout for byte/word write 2 n times typical 24h 0005h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses (x16) data description 27h 0017h device size = 2 n byte 28h 29h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0001h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 007fh 0000h 0000h 0001h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
94 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information table 8. primary vendor-s pecific extended query command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. tables 10 and 11 define the valid register command sequences. writing incorrect address and data values or writing them in the improper se- quence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any addresses (x16) data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0008h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 0.23 m mirrorbit 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0001h page mode type 00 = not supported, 01 = 4 word/8 byte page, 02 = 8 word/16 byte page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0004h/ 0005h top/bottom boot sector flag 00h = uniform device without wp# protect, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h 0001h program suspend 00h = not supported, 01h = supported
november 24, 2003 am70pdl127cdh/am70pdl129cdh 95 advance information non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. see the next section, reset command , for more informa- tion. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 14 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer pro- gramming operation, the system must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: note: the device id is read over three cycles. sa = sector address ta bl e s 10 and 11 show the address requirements and codes. the autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively pro- gramming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend). enter secsi sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-word/16-byte random electronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system is- sues the four-cycle exit secsi sector command se- quence. the exit secsi sector command sequence returns the device to normal operation. tables 10 and 11 show the address and data requirements for both command sequences. see also ?secsi (secured sili- con) sector flash memory region? for further informa- tion. note that the acc function and unlock bypass modes are not available when the secsi sector is en- abled. word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further identifier code a7:a0 (x16) manufacturer id 00h device id, cycle 1 01h device id, cycle 2 0eh device id, cycle 3 0fh secsi sector factory protect 03h sector protect verify (sa)02h
96 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. tables 10 and 11 show the address and data requirements for the word/byte pro- gram command sequence, respectively. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7 or dq6. refer to the write operation status sec- tion for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing two un- lock cycles. this is followed by a third write cycle con- taining the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle un- lock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program com- mand, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. tables 10 and 11 show the requirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the device then returns to the read mode. write buffer programming write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initi- ated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which pro- gramming will occur. the fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. for example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is se- lected by address bits a max ?a 4 . all subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer locations may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be per- formed across multiple write-buffer pages. this also means that write buffer programming cannot be per- formed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. note that if a write buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. the host system must therefore account for loading a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the pro- gram buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming operation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming.
november 24, 2003 am70pdl127cdh/am70pdl129cdh 97 advance information the write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: load a value that is greater than the page buffer size during the number of locations to program step. write to an address in a sector different than the one specified during the write-buffer-load com- mand. write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data load- ing stage of the operation. write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset command sequence must be written to reset the de- vice for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is re- quired when using write-buffer-programming features in unlock bypass mode. accelerated program the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerated programming, or device dam- age may result. in addition, no external pullup is nec- essary since the wp#/acc pin has internal pullup to v cc . figure 5 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 17 for timing diagrams.
98 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information figure 4. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write-buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see table 11 for command sequences required for write buffer programming. (note 3) (note 1) (note 2)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 99 advance information figure 5. program operation program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when the program sus- pend command is written during a programming pro- cess, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not required when writing the program suspend command. after the programming operation has been sus- pended, the system can read array data from any non-suspended sector. the program suspend com- mand may also be issued during a programming oper- ation while an erase is suspended. in this case, data may be read from any addresses not in erase sus- pend or program suspend. if a read is needed from the secsi sector area (one-time program area), then user must use the proper command sequences to enter and exit this region. note that the secsi sector, autoselect, and cfi functions are unavailable when an program operation is in progress. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autose- lect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. after the program resume command is written, the device reverts to programming. the system can de- termine the status of the program operation using the dq7 or dq6 status bits, just as in the standard pro- gram operation. see write operation status for more information. the system must write the program resume com- mand (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ig- nored. another program suspend command can be written after the device has resume programming. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see ta bl e 1 1 for program command sequence.
100 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information figure 6. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. tables 10 and 11 show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for infor- mation on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. note that the secsi sector, autoselect, and cfi functions are un- available when an erase operation is in progress. figure 7 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 19 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. tables 10 and 11 show the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must re- write the command sequence and any additional ad- dresses and commands. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
november 24, 2003 am70pdl127cdh/am70pdl129cdh 101 advance information the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write opera- tion status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 7 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 19 section for timing diagrams. figure 7. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sec- tor erase operation, including the 50 s time-out pe- riod during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 (typical 5 s) to suspend the erase opera- tion. however, when the erase suspend command is written during the sector erase time-out, the device im- mediately terminates the time-out period and sus- pends the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writ- ing this command. further writes of the resume com- mand are ignored. another erase suspend command can be written after the chip has resumed erasing. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see tables 10 and 11 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
102 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information command definitions table 9. command definitions (x16 mode) legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address . addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. wbl = write buffer location. address must be within same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see ta bl e 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or 2aa as shown in table, address bits above a11 and data bits above dq7 are don?t care. 5. no unlock or command cycles required when device is in read mode. 6. reset command is required to return to read mode (or to erase-suspend-read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 7. fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. except for rd, pd and wc. see autoselect command sequence section for more information. 8. device id must be read in three cycles. 9. wp# protects highest address sector, data is 98h for factory locked and 18h for not factory locked. data is 00h for an unprotected sector group and 01h for a protected sector group. 10. total number of cycles in command sequence is determined by number of words written to write buffer. maximum number of cycles in command sequence is 21. 11. command sequence resets device for next command after aborted write-to-buffer operation. 12. unlock bypass command is required prior to unlock bypass program command. 13. unlock bypass reset command is required to return to read mode when device is in unlock bypass mode. 14. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend command is valid only during a sector erase operation. 15. erase resume command is valid only during erase suspend mode. 16. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 8) 6 555 aa 2aa 55 555 90 x01 227e x0e 220c x0f 2201 secsi ? sector factory protect (note 9) 4 555 aa 2aa 55 555 90 x03 (note 10) sector group protect verify (note 10) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (note 11) 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 12) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 13) 2 xxx a0 pa pd unlock bypass reset (note 14) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 15) 1 ba b0 program/erase resume (note 16) 1 ba 30 cfi query (note 17) 1 55 98
november 24, 2003 am70pdl127cdh/am70pdl129cdh 103 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 12 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is com- plete or in progress. the device also provides a hard- ware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on suc- cessive read cycles. table 12 shows the outputs for data# polling on dq7. figure 8 shows the data# polling algorithm. figure 20 in the ac characteristics section shows the data# polling timing diagram. figure 8. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
104 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. ta bl e 1 2 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the de- vice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alterna- tively, the system can use dq7 (see the subsection on dq7: data# polling ). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 12 shows the outputs for toggle bit i on dq6. figure 9 shows the toggle bit algorithm. figure 21 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 22 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii .
november 24, 2003 am70pdl127cdh/am70pdl129cdh 105 advance information figure 9. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 12 to compare out- puts for dq2 and dq6. figure 9 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/busy# sub- section. figure 21 shows the toggle bit timing diagram. figure 22 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 9 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
106 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 9). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not suc- cessfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 12 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort-reset command sequence to re- turn the device to reading array data. see write buffer table 10. write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
november 24, 2003 am70pdl127cdh/am70pdl129cdh 107 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 , oe#, acc, and reset# (note 2) . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 10. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 11. 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10. maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7?3.1 v v io (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7?3.1 v notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 10. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 11. maximum positive overshoot waveform
108 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maximum input load current when wp# = v il is 5.0 a. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. if v io < v cc , maximum v il for ce# and dq i/os is 0.3 v io . if v io < v cc , minimum v ih for ce# and dq i/os is 0.7 v io . maximum v ih for these connections is v io + 0.3 v. 7. v cc voltage requirements. 8. v io voltage requirements. 9. includes ry/by# 10. not 100% tested. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit acc input load current v cc = v cc max 35 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (2, 3) ce# = v il, oe# = v ih , 5 mhz 15 20 ma 1 mhz 15 20 i cc2 v cc initial page read current (2, 3) ce# = v il, oe# = v ih 30 50 ma i cc3 v cc intra-page read current (2, 3) ce# = v il, oe# = v ih 10 20 ma i cc4 v cc active write current (3, 4) ce# = v il, oe# = v ih 50 60 ma i cc5 v cc standby current (3) ce#, reset# = v cc 0.3 v, wp# = v ih 15a i cc6 v cc reset current (3) reset# = v ss 0.3 v, wp# = v ih 15a i cc7 automatic sleep mode (3, 5) v ih = v cc 0.3 v; v il = v ss 0.3 v, wp# = v ih 15a v il1 input low voltage 1(6, 7) ?0.5 0.8 v v ih1 input high voltage 1 (6, 7) 1.9 v cc + 0.5 v v il2 input low voltage 2 (6, 8) ?0.5 0.3 x v io v v ih2 input high voltage 2 (6, 8) 1.9 v io + 0.5 v v hh voltage for acc program acceleration v cc = 2.7 ?3.3 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.3 v 11.5 12.5 v v ol output low voltage (9) i ol = 2.0 ma, v cc = v cc min = v io 0.15 x v io v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min = v io 0.85 v io v v oh2 i oh = ?100 a, v cc = v cc min = v io v io ?0.4 v v lko low v cc lock-out voltage (10) 2.3 2.5 v
november 24, 2003 am70pdl127cdh/am70pdl129cdh 109 advance information test conditions table 11. test specifications note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms 2.7 k ? c l 6.2 k ? 3.1 v device under te s t note: diodes are in3064 or equivalent figure 12. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels (see note) 1.5 v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 0.5 v io v output measurement level input note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 13. input waveforms and measurement levels
110 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 12 and table 13 for test specifications. 3. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter description test setup all speed options jedec std. unit t avav t rc read cycle time (note 1) min 110 ns t avqv t acc address to output delay ce#, oe# = v il max 110 ns t elqv t ce chip enable to output delay oe# = v il max 110 ns t pa c c page access time max 30 ns t glqv t oe output enable to output delay max 30 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce data we# addresses ce# or ce2# oe# high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 14. read operation timings
november 24, 2003 am70pdl127cdh/am70pdl129cdh 111 advance information ac characteristics * figure shows device in word mode. addresses are a1?a-1 for byte mode. figure 15. page read timings a21 - a2 ce# oe# a1 - a0 data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
112 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information ac characteristics hardware reset (reset#) notes: 1. not 100% tested. 2. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready c e# or ce2#, oe# t rh c e# or ce2#, oe# reset timings during embedded algorithms reset# t rp t rb figure 16. reset timings
november 24, 2003 am70pdl127cdh/am70pdl129cdh 113 advance information ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. word/byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter all speed options jedec std. description unit t avav t wc write cycle time (note 1) min 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 352 s effective write buffer program operation (notes 2, 4) per byte typ 11 s per word typ 22 s accelerated effective write buffer program operation (notes 2, 4) per byte typ 8.8 s per word typ 17.6 s single word/byte program operation (note 2, 5) byte ty p 100 s word 100 single word/byte accelerated programming operation (note 2, 5) byte ty p 90 word 90 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy we# high to ry/by# low min 110 ns
114 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information ac characteristics oe# we# ce# or ce2# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 17. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 18. accelerated program timing diagram
november 24, 2003 am70pdl127cdh/am70pdl129cdh 115 advance information ac characteristics oe# ce# or ce2# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch status d out t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?. 2. illustration shows device in word mode. figure 19. chip/sector erase operation timings
116 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information ac characteristics we# ce# or ce2# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 20. data# polling timings (during embedded algorithms)
november 24, 2003 am70pdl127cdh/am70pdl129cdh 117 advance information ac characteristics oe# ce# or ce2# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 21. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 22. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
118 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information ac characteristics temporary sector unprotect notes: 1. not 100% tested. 2. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s reset# t vidr v id v il or v ih v id v il or v ih c e# or ce2# we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 23. temporary sector group unprotect timing diagram
november 24, 2003 am70pdl127cdh/am70pdl129cdh 119 advance information ac characteristics sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a3, a2, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih * for sector group protect, a6:a0 = 0xx0010. for sector group unprotect, a6:a0 = 1xx0010. figure 24. sector group protect and unprotect timing diagram
120 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. word/byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter speed options jedec std. description unit t avav t wc write cycle time (note 1) min 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 352 s effective write buffer program operation (notes 2, 4) per word typ 22 s s accelerated effective write buffer program operation (notes 2, 4) per word typ 17.6 s s single word/byte program operation (note 2, 5) word typ 100 s single word/byte accelerated programming operation (note 2, 5) word typ 90 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t rh reset# high time before write min 50 ns
november 24, 2003 am70pdl127cdh/am70pdl129cdh 121 advance information t ghel t ws oe# ce# or ce2# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. illustration shows device in word mode. figure 25. alternate ce# controlled write (erase/program) operation timings
122 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc . programming specifications assume that all bits are programmed to 00h. 2. maximum values are measured at v cc = 3.0 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. word programming specification is based upon a single word programming operation not utilizing the write buffer. 4. for 1-16 words programmed in a single write buffer programming operation. 5. effective write buffer specification is calculated on a per-word basis for a 16-word write buffer operation. 6. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 7. system-level overhead is the time required to execute the command sequence(s) for the program command. see tables 12 and 11 for further information on command definitions. 8. the device has a minimum erase and program cycle endurance of 100,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 15 sec chip erase time 32 128 sec single word program time (note 3) word 100 tbd s accelerated single word program time (note 3) word 90 tbd s total write buffer program time (note 4) 352 tbd s effective write buffer program time (note 3) per word 22 tbd s total accelerated effective write buffer program time (note 4) 282 tbd s effective accelerated write buffer program time (note 4) word 17.6 tbd s chip program time 92 tbd sec description min max input voltage with respect to v ss on all pins except i/o pins (including oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma
november 24, 2003 am70pdl127cdh/am70pdl129cdh 123 advance information package pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 11 26 pf c out output capacitance v out = 0 12 28 pf c in2 control pin capacitance v in = 0 14 28 pf c in3 wp#/acc pin capacitance v in = 0 17 20 pf
124 am70pdl127cdh/am70pdl129cdh november 24, 2003 advance information physical dimensions fua093?93-ball fine-pitch grid array 13 x 9 mm package 3300 \ 16-038.21a package fua 093 jedec n/a 13.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.40 profile a1 0.16 --- --- ball height a2 1.06 --- 1.21 body thickness d 13.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 93 ball count b 0.31 --- 0.41 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9,c10,d1,d10, depopulated solder balls e1,e10,h1,h10,j1,j10,k1,k10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 index mark 93x c 0.15 (2x) (2x) c 0.15 b a 6 b 0.20 c c d e pin a1 c top view side view corner a2 a1 a 0.08 0.15 m c mc ab 0.08 10 8 9 7 6 4 3 2 1 5 a dc e f g h j k l m b ed corner e1 7 se d1 ee sd bottom view pin a1 7
november 24, 2003 am70pdl127cdh/am70pdl129cdh 125 advance information revision summary revision a (august 16, 2003) initial release. revision a+1 (september 3, 2003) connection diagrams corrected ball grid labels for balls k9 and l7?l9 on both am70pdl127cdh and am70pdl129cdh con- nection diagrams. revision a+2 (november 24, 2003) device information removed reference to page mode for psram. distinctive characteristics, flash memory features (data storage) removed reference to v io . product selector guide corrected psram access times. operating ranges corrected v cc f/v cc s standard voltage range max from 3.3 v to 3.1 v. dc characteristics test condition i ol of v ol updated from 4.0 ma to 2.0 ma. test conditions corrected max voltage from 3.3 v to 3.1 v. secsi tm (secured silicon) sector flash memory region customer lockable area (64 words): clarified text under first bullet and added secsi sector protection algorithm figure. table 17, sector protection command definitions corrected number of cycles for secsi protection bit status, ppmlb status, and spmlb status to 5 cycles. for these command sequences, inserted a cycle be- fore the final read cycle (rd0). psram ac characteristics corrected speed bins to 66/85 ns. trademarks copyright ? 2003 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are r egistered trademarks of advanced micro devices, inc.

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